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| TMP1962C10BXBG 2006-02-21 tmp1962-1 32-bit risc microprocessor tx19 family TMP1962C10BXBG 1. features the tx19 is a family of high-perfo rmance 32-bit microprocessors that offers the speed of a 32-bit risc solution with the added advantage of a significantly reduce d code size of a 16-bit archit ecture. the instruction set of the tx19 includes as a subset the 32-bit instructions of the tx39, which is based on the mips r3000a tm architecture. additionally, the tx19 supports the mips16 tm application-specific extensions (ase) for improved code density. the tmp1962 is built on a tx19 core processor and a selection of intelligent peripherals. the tmp1962 is suitable for low-voltage, low-power applications. features of the tmp196 2 include the following: (1) tx19 core processor 1) two instruction set architecture (isa) modes: 16-bit isa for code density and 32-bit isa for speed ? the 16-bit isa is object-code compatible with the code-efficient mips16 tm ase. ? the 32-bit isa is object-cod e compatible with the hi gh-performance tx39 family. 2) combines high performance with low power consumption. ? high performance ? single clock cycle execution for most instructions ? 3-operand computational instructions for high instruction throughput ? 5-stage pipeline ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the third parties which may re sult from its use. no license is gran ted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their i nherent electrical sensitivity and vu lnerability to physical stress. it is the re sponsibility of the buyer, when utilizing toshiba products, to comply with the st andards of safety in making a safe design for the entire syste m, and to avoid situations in which a malfuncti on or failure of such toshiba products could cause loss of human life, bodily inju ry or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specificati ons. also, please keep in mind the precauti ons and conditions set forth in the ?handlin g guide for semiconductor devices,? or ?tos hiba semiconductor reli ability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics appl ications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances , etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ctionor failure of which may cause loss of human life or bodily in jury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instrum ents, traffic signal instruments, combustion con trol instruments, medical instruments, all types of safety devices , etc.. unintended usage of toshiba pr oducts listed in this docume nt shall be made at the customer?s own risk. ? the products described in this document are s ubject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. ? for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/handling precautions. 030619ebp
TMP1962C10BXBG 2006-02-21 tmp1962-2 ? on-chip high-speed memory ? dsp function: executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single clock cycle. ? low power consumption ? optimized design using a low-power cell library ? programmable standby modes in which processor clocks are stopped 3) fast interrupt response suitable for real-time control ? distinct starting locations for each interrupt service routine ? automatically generated vector s for each interrupt source ? automatic updates of the interrupt mask level (2) on-chip program memory and data memory product on-chip rom on-chip ram tmp1962c10axb 1 mbyte 40 kbyte tmp1962f10axb 1 mbyte (flash) 40 kbyte ? rom correction logic (8 words x 8 blocks) (3) external memory expansion ? 16-mbyte off-chip address space for code and data ? external data bus separate bus/multiplexed bus: dynamic bus sizing for 8-bit and 16-bit data ports (4) 8-channel dma controller ? interrupt- or software-triggered ? transfer destination: on-chip memory, on-chip peripherals, external memory, external peripherals (5) 12-channel 8-bit timer ? 8/16/24/32-bit interval timer mode ? 8-bit pwm mode ? 8-bit ppg mode (6) 4-channel 16-bit timer ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit ppg output ? input capture ? 2-phase pulse input counter (2 channels) TMP1962C10BXBG 2006-02-21 tmp1962-3 (7) 32-bit input capture ? 32-bit input capture registers (8 channels) ? 32-bit compare registers (8 channels) ? 32-bit time base timer (1 channel) (8) 7-channel general-purpose serial interface ? either uart mode or synchronous mode can be selected. (9) 1-channel serial bus interface ? either i 2 c bus mode or clock-synchronous mode can be selected. (10) 24-channel 10-bit a/d converter (with internal sample/hold) ? external trigger supported ? fixed-channel or channel scan mode ? single conversion or continuous conversion mode ? timer monitoring (11) 1-channel watchdog timer (12) 4-channel chip select/wait controller (13) interrupt sources ? 4 cpu interrupts: software interrupt instruction ? 55 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt ? 25 external interrupts: 7 priority levels, with the exception of the nmi interrupt the external sources include 14 kwup sources, which are all assigned to a single interrupt vector. (14) 202-pin input/output ports (15) standby modes ? two standby modes: idle, stop (16) clock generator ? on-chip pll (x3) ? clock gear: divides the high-speed clock by 1/2, 1/4 or 1/8. TMP1962C10BXBG 2006-02-21 tmp1962-4 (17) optional big-endian alignment big-endian higher address 31 24 23 16 15 8 7 0 word address 8 9 10 11 8 4 5 6 7 4 0 1 2 3 0 lower address ? byte 0 is the highest-order byte (bits 31-24). ? the address of a word data item is the address of its highest-order byte (byte 0). little-endian higher address 31 24 23 16 15 8 7 0 word address 11 10 9 8 8 7 6 5 4 4 3 2 1 0 0 lower address ? byte 0 is the lowest-order byte (bits 7-0). ? the address of a word data item is the address of its lowest-order byte (byte 0). (18) operating frequency ? 40.5 mhz (vcc = 1.35 v to 1.65 v) (19) package ? p-fbga281 (13 mm x 13 mm, 0.65-mm pitch) TMP1962C10BXBG 2006-02-21 tmp1962-5 figure 1.1 tmp1962 block diagram tx19 processor core tx19 cpu mac dsu 1 mbyte flash rom 40 kbyte ram rom correction dmac (8ch) cg intc ebif i/o bus i/f 8-bit tmra 0/1 to a/b (12ch) 16-bit tmrb 0 to 3(4ch) 32-bit tmrc tbt(1ch) 32-bit tmrc input capture 0 to 7 (8ch) 32-bit tmrc compare 0 to 7 (8ch) 10-bit adc (24ch) sio 0 to 6 (7ch) i 2 c (1ch) port0 to port6 (shared with external bus interface) wdt kwup 0 to d (14ch) port7 to port9 (shared with adc input) porta to portl, portn (shared with functional pins) portm, porto to portp (general-purpose ports) TMP1962C10BXBG 2006-02-21 tmp1962-6 2. signal descriptions this section contains pin assignments for the tmp1962 as well as brief descriptions of the tmp1962 input and output signals. 2.1 pin assignment (top view) the following illustrates the tmp1962 pin assignment. figure 2.1 p-fbga281 pin assignment table 2.1 shows the correspondence between the numbers and names of the tmp1962 pins. table 2.1 pin numbers and names (1/2) pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 nc a13 pk1/key1 b8 p75/ain5 c2 pcst3 (dsu) c14 pk6/key6 a2 vrefl a14 pi1/int1 b9 pl0/ta4in c3 p92/ain18 c15 pi5/int9 a3 p90/ain16 a15 pi3/int3 b10 pl3/taain c4 p95/ain21 c16 tck (jtag) a4 p93/ain19 a16 pi6/inta b11 pm1 c5 p82/ain10 c17 cvcc15 (cvcc2) a5 p80/ain8 a17 x2 b12 pm4 c6 p85/ain13 c18 nc (xt2) a6 p83/ain11 b1 avcc31 b13 pk2/key2 c7 p72/ain2 d1 sdao/tpc (dsu) a7 p70/ain0 b2 vrefh b14 pi2/int2 c8 avss d2 pcst2 (dsu) a8 p74/ain4 b3 p91/ain17 b15 pi4/int4 c9 pl1/ta6in d3 sdi/ dint (dsu) a9 nc b4 p94/ain20 b16 pi7 c10 pl4/tb0in0 d4 dvcc15 (dvcc22) a10 pl2/ta8in b5 p81/ain9 b17 cvss c11 pm2 d5 p96/ain22 a11 pm0 b6 p84/ain12 b18 x1 c12 pm5 d6 p86/ain14 a12 pk0/key0 b7 p71/ain1 c1 pcst0 (dsu) c13 pk3/key3 d7 p73/ain3 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 e14 e15 e16 e17 e18 f1 f2 f3 f4 f5 f7 f8 f9 f10 f11 f12 f14 f15 f16 f17 f18 g1 g2 g3 g4 g5 g6 g13 g14 g15 g16 g17 g18 h1 h2 h3 h4 h5 h6 h13 h14 h15 h16 h17 h18 j1 j2 j3 j4 j5 j6 j13 j14 j15 j16 j17 j18 k1 k2 k3 k4 k5 k6 k13 k14 k15 k16 k17 k18 l1 l2 l3 l4 l5 l6 l13 l14 l15 l16 l17 l18 m1 m2 m3 m4 m5 m6 m13 m14 m15 m16 m17 m18 n1 n2 n3 n4 n5 n7 n8 n9 n10 n11 n12 n14 n15 n16 n17 n18 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 TMP1962C10BXBG 2006-02-21 tmp1962-7 table 2.1 pin numbers and names (2/2) pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name d8 dvcc15 (dvcc22) f18 p44/scout k14 p12/d10/ad10 n18 dvss t8 pd4/txd4 d9 dvss g1 reset k15 p13/d11/ad11 p1 pp0 t9 pc0/txd0 d10 pl5/tb0in1 g2 test5 k16 p14/d12/ad12 p2 pb2/tb2in0/int5 t10 pc3/txd1 d11 pm3 g3 dvcc2 (fvcc2) k17 dvcc33 p3 pb3/tb2in1/int6 t11 ph4/tcout4 d12 pm6 g4 nc (fvss) k18 p15/d13/ad13 p4 pb4/tb2out t12 pe2/sclk5/ 5cts d13 pk4/key4 g5 pj0/int0 l1 nc (fvcc3) p5 pb5/tb3in0/int7 t13 pe5/keyb d14 pk7/key7 g6 bw0 l2 po1 p6 pg5/tc5in t14 p53/a3 d15 dvcc34 g13 trst l3 po2 p7 pg7/tc7in t15 p56/a6 d16 tdi (jtag) g14 nc (cap1) l4 po3 p8 pd6/sclk4/ 4cts t16 p62/a10 d17 tdo (jtag) g15 p41/ 1cs l5 po4 p9 pc2/sclk0/ 0cts t17 p65/a13 d18 nc (xt1) g16 p37/ale l6 po7 p10 pc5/sclk1/ 1cts t18 p20/a16/a0 e1 dclk (dsu) g17 p35/ busak l13 nc (test3) p11 ph6/tcout6 u1 pa0/ta0in e2 pcst1 (dsu) g18 nc (fvcc2) l14 p06/d6/ad6 p12 nc u2 pa3/ta3out e3 dbge h1 nmi l15 nc (fvcc2) p13 p50/a0 u3 pa6/ta9out e4 pj3/intlv h2 dvcc31 l16 p07/d7/ad7 p14 p51/a1 u4 pf1/si/scl e5 pj4/endian h3 pn7 l17 p10/d8/ad8 p15 p54/a4 u5 pf5/ 3dreq e6 p97/ain23 h4 bw1 l18 p11/d9/ad9 p16 p23/a19/a3 u6 pg2/tc2in e7 p87/ain15 h5 plloff m1 po0 p17 p24/a20/a4 u7 pd2/rxd3 e8 p76/ain6 h6 nc (test1) m2 pp5 p18 p25/a21/a5 u8 dvcc32 e9 p77/ain7 h13 nc (test2) m3 pp6 r1 pb0/tb0out u9 pc7/rxd2 e10 pl6/tb1in0 h14 p31/ wr m4 pp7 r2 pb1/tb1out u10 ph1/tcout1 e11 pl7/tb1in1 h15 p32/ hwr m5 pb7/tb3out r3 pf3/ 2dreq u11 ph3/tcout3 e12 pm7 h16 p33/wait/rdy m6 dvcc32 r4 pf4/ 2dack u12 pe1/rxd5 e13 pk5/key5 h17 p30/ rd m13 nc (test4) r5 pf7/tbtin u13 pe4/keya e14 nc h18 p40/ 0cs m14 p02/d2/ad2 r6 pg4/tc4in u14 dvcc32 e15 tms (jtag) j1 pn2/sclk6/ 6cts m15 nc (fvss) r7 pg6/tc6in u15 p57/a7 e16 nc (cvcch) j2 pn3 m16 p03/d3/ad3 r8 pd5/rxd4 u16 p63/a11 e17 nc j3 pn4 m17 p04/d4/ad4 r9 pc1/rxd0 u17 p66/a14 e18 dvcc15 (dvcc22) j4 pn5 m18 p05/d5/ad5 r10 pc4/rxd1 u18 dvcc33 f1 dvss j5 pn6 n1 pp1 r11 ph5/tcout5 v2 pa2/ta2in f2 dreset j6 dvcc15 (dvcc22) n2 pp2 r12 ph7/tcout7 v3 pa5/ta7out f3 sysrdy j13 nc (fvss) n3 pp3 r13 pe6/keyc v4 pf0/so/sda f4 pj1/busmd j14 p16/d14/ad14 n4 pp4 r14 p52/a2 v5 pg0/tc0in f5 pj2/ boot j15 dvss n5 pb6/tb3in1/int8 r15 p55/a5 v6 pg1/tc1in f7 avss j16 p17/d15/ad15 n7 dvss r16 p61/a9 v7 pd1/txd3 f8 avss j17 p36/ w/r n8 pd7/key8 r17 p21/a17/a1 v8 pd0/sclk2/ 2cts f9 avcc32 j18 p34/ busrq n9 dvcc15 (dvcc22) r18 p22/a18/a2 v9 pc6/txd2 f10 dvcc34 k1 pn0/txd6 n10 dvss t1 pa1/ta1out v10 ph0/tcout0 f11 pi0/ adtrg k2 pn1/rxd6 n11 rstpup t2 pa4/ta5out v11 ph2/tcout2 f12 dvss k3 po5 n12 dvss t3 pa7/tabout v12 pe0/txd5 f14 nc (cap2) k4 po6 n14 p26/a22/a6 t4 pf2/sck v13 pe3/key9 f15 p42/ 2cs k5 nc (fvss) n15 p27/a23/a7 t5 pf6/ 3dack v14 pe7/keyd f16 p43/ 3cs k6 dvss n16 p00/d0/ad0 t6 pg3/tc3in v15 p60/a8 f17 dvcc33 k13 nc (test0) n17 p01/d1/ad1 t7 pd3/sclk3/ 3cts v16 p64/a12 v17 p67/a15 note : parentheses indicate the pin name on tmp1962f10axbg with on-chip flash memory. (except ?dsu? and ?jtag?. the same pin names are used for the on-chip mask rom type and on-chip flash memory type.) TMP1962C10BXBG 2006-02-21 tmp1962-8 2.2 pin usage information table 2.2 lists the input and output pins of the tmp1962, including alternate pin names and functions for multi-function pins. table 2.2 pin names and functions (1/6) pin name number of pins type function p00 - p07 d0 - d7 ad0 - d7 8 input/output input/output input/output port 0: individually programmable as input or output data (lower): bits 0 to 7 of the data bus (separate bus mode) address/data (lower): bits 0 to 7 of the address/data bus (multiplexed bus mode) p10 - p17 d8 - d15 ad8 - ad15 a8 - a15 8 input/output input/output input/output output port 1: individually programmable as input or output data (upper): bits 8 to 15 of the data bus (separate bus mode) address/data (upper): bits 8 to 15 of the address/data bus (multiplexed bus mode) address: bits 8 to 15 of the address bus (multiplexed bus mode) p20 - p27 a16 - a23 a0 - a7 a16 - a23 8 input/output output output output port 2: individually programmable as input or output address: bits 16 to 23 of the address bus (separate bus mode) address: bits 0 to 7 of the address bus (multiplexed bus mode) address: bits 16 to 23 of the address bus (multiplexed bus mode) p30 rd 1 output output port 30: output-only read strobe: asserted during a read operati on from an external memory device p31 wr 1 output output port 31: output-only write strobe: asserted during a write operation on d0 to d7 p32 hwr 1 input/output output port 32: programmable as input or output (with internal pull-up resistor) higher write strobe: asserted during a write operation on d8 to d15 p33 wait rdy 1 input/output input input port 33: programmable as input or output (with internal pull-up resistor) wait: causes the cpu to sus pend external bus activity ready: notifies the cpu that the bus is ready p34 busrq 1 input/output input port 34: programmable as input or output (with internal pull-up resistor) bus request: asserted by an external bus master to request bus mastership p35 busak 1 input/output output port 35: programmable as input or output (with internal pull-up resistor) bus acknowledge: indicates that the cpu has relinquished the bus in response to busrq p36 w/r 1 input/output output port 36: programmable as input or output (with internal pull-up resistor) read/write: indicates the direction of data transfer on the bus: 1 = read or dummy cycle, 0 = write cycle p37 ale 1 input/output output port 37: programmable as input or output address latch enable (enabled only when an ex ternal memory device is accessed) p40 0cs 1 input/output output port 40: programmable as input or output (with internal pull-up resistor) chip select 0: asserted low to enable external devices at programmed addresses p41 1cs 1 input/output output port 41: programmable as input or output (with internal pull-up resistor) chip select 1: asserted low to enable external devices at programmed addresses p42 2cs 1 input/output output port 42: programmable as input or output (with internal pull-up resistor) chip select 2: asserted low to enable external devices at programmed addresses p43 3cs 1 input/output output port 43: programmable as input or output (with internal pull-up resistor) chip select 3: asserted low to enable external devices at programmed addresses p44 scout 1 input/output output port 44: programmable as input or output system clock output: drives out a clock signal at the same frequency as the cpu clock (high-speed or low-speed) or half the high-speed clock frequency p50 - p57 a0 - a7 8 input/output output port 5: individually programmable as input or output address: bits 0 to 7 of the address bus (separate bus mode) p60 - p67 a8 - a15 8 input/output output port 6: individually programmable as input or output address: bits 8 to 15 of the address bus (separate bus mode) TMP1962C10BXBG 2006-02-21 tmp1962-9 table 2.2 pin names and functions (2/6) pin name number of pins type function p70 - p77 an0 - an7 8 input input port 7: input-only analog input: input to the on-chip a/d converter p80 - p87 an8 - an15 8 input input port 8: input-only analog input: input to the on-chip a/d converter p90 - p97 an16 - an23 8 input input port 9: input-only analog input: input to the on-chip a/d converter pi0 adtrg 1 input/output input port i0: programmable as input or output a/d trigger: starts an a/d conversion schmitt-triggered input pi1 int1 1 input/output input port i1: programmable as input or output interrupt request 1: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt-triggered input pi2 int2 1 input/output input port i2: programmable as input or output interrupt request 2: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt-triggered input pi3 int3 1 input/output input port i3: programmable as input or output interrupt request 3: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt-triggered input pi4 int4 1 input/output input port i4: programmable as input or output interrupt request 4: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt-triggered input pi5 int9 1 input/output input port i5: programmable as input or output interrupt request 9: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt-triggered input pi6 inta 1 input/output input port i6: programmable as input or output interrupt request a: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt-triggered input pi7 1 input/output port i7: programmable as input or output pa0 ta0in 1 input/output input port a0: programmable as input or output 8-bit timer 0 input: input to 8-bit timer 0 pa1 ta1out 1 input/output output port a1: programmable as input or output 8-bit timer 01 output: output from either 8-bit timer 0 or 1 pa2 ta2in 1 input/output input port a2: programmable as input or output 8-bit timer 2 input: input to 8-bit timer 2 pa3 ta3out 1 input/output output port a3: programmable as input or output 8-bit timer 23 output: output from either 8-bit timer 2 or 3 pa4 ta5out 1 input/output output port a4: programmable as input or output 8-bit timer 45 output: output from either 8-bit timer 4 or 5 pa5 ta7out 1 input/output output port a5: programmable as input or output 8-bit timer 67 output: output from either 8-bit timer 6 or 7 pa6 ta9out 1 input/output input port a6: programmable as input or output 8-bit timer 89 output: output from either 8-bit timer 8 or 9 pa7 tabout 1 input/output output port a7: programmable as input or output 8-bit timer ab output: output from either 8-bit timer a or b pb0 tb0out 1 input/output output port b0: programmable as input or output 16-bit timer 0 output: output from 16-bit timer 0 pb1 tb1out 1 input/output output port b1: programmable as input or output 16-bit timer 1 output: output from 16-bit timer 1 TMP1962C10BXBG 2006-02-21 tmp1962-10 table 2.2 pin names and functions (3/6) pin name number of pins type function pb2 tb2in0 int5 1 input/output input input port b2: programmable as input or output 16-bit timer 2 input 0: count/capture trigger input to 16-bit timer 2 interrupt request 5: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb3 tb2in1 int6 1 input/output input input port b3: programmable as input or output 16-bit timer 2 input 1: capture trigger input to 16-bit timer 2 interrupt request 6: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb4 tb2out 1 output output port b4: programmable as input or output 16-bit timer 2 output: output from 16-bit timer 2 pb5 tb3in0 int7 1 output input input port b5: programmable as input or output 16-bit timer 3 input 0: count/capture trigger input to 16-bit timer 3 interrupt request 7: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb6 tb3in1 int8 1 output input input port b6: programmable as input or output 16-bit timer 3 input 1: capture trigger input to 16-bit timer 3 interrupt request 8: programmable to be high-level, low-level, rising-edge or falling-edge sensitive pb7 tb3out 1 output output port b7: programmable as input or output 16-bit timer 3 output: output from 16-bit timer 3 pc0 txd0 1 input/output output port c0: programmable as input or output serial transmit data 0: programmabl e as a push-pull or open-drain output pc1 rxd0 1 input/output input port c1: programmable as input or output serial receive data 0 pc2 sclk0 0cts 1 input/output input input port c2: programmable as input or output serial clock input/output 0 serial clear-to-send 0: programmabl e as a push-pull or open-drain output pc3 txd1 1 input/output output port c3: programmable as input or output serial transmit data 1: programmabl e as a push-pull or open-drain output pc4 rxd1 1 input/output input port c4: programmable as input or output serial receive data 1 pc5 sclk1 1cts 1 input/output input input port c5: programmable as input or output serial clock input/output 1 serial clear-to-send 1: programmabl e as a push-pull or open-drain output pc6 txd2 1 input/output output port c6: programmable as input or output serial transmit data 2: programmabl e as a push-pull or open-drain output pc7 rxd2 1 input/output input port c7: programmable as input or output serial receive data 2 pd0 sclk2 2cts 1 input/output input input port d0: programmable as input or output serial clock input/output 2 serial clear-to-send 2: programmabl e as a push-pull or open-drain output pd1 txd3 1 input/output output port d1: programmable as input or output serial transmit data 3: programmabl e as a push-pull or open-drain output pd2 rxd3 1 input/output input port d2: programmable as input or output serial receive data 3 pd3 sclk3 3cts 1 input/output input input port d3: programmable as input or output serial clock input/output 3 serial clear-to-send 3: programmabl e as a push-pull or open-drain output pd4 txd4 1 input/output output port d4: programmable as input or output serial transmit data 4: programmabl e as a push-pull or open-drain output pd5 rxd4 1 input/output input port d5: programmable as input or output serial receive data 4 pd6 sclk4 4cts 1 input/output input input port d6: programmable as input or output serial clock input/output 4 serial clear-to-send 4: programmabl e as a push-pull or open-drain output pd7 key8 1 input/output input port d7: programmable as input or output key-pressed wake-up input 8 (with internal pull-up resistor): dynamic pull-up selectable schmitt-triggered input TMP1962C10BXBG 2006-02-21 tmp1962-11 table 2.2 pin names and functions (4/6) pin name number of pins type function pe0 txd5 1 input/output output port e0: programmable as input or output serial transmit data 5: programmabl e as a push-pull or open-drain output pe1 rxd5 1 input/output input port e1: programmable as input or output serial receive data 5 pe2 sclk5 5cts 1 input/output input input port e2: programmable as input or output serial clock input/output 5 serial clear-to-send 5: programmabl e as a push-pull or open-drain output pe3 key9 1 input/output input port e3: programmable as input or output key-pressed wake-up input 9 (with internal pull-up resistor): dynamic pull-up selectable schmitt-triggered input pe4 keya 1 input/output input port e4: programmable as input or output key-pressed wake-up input a (with internal pull-up resistor): dynamic pull-up selectable schmitt-triggered input pe5 keyb 1 input/output input port e5: programmable as input or output key-pressed wake-up input b (with internal pull-up resistor): dynamic pull-up selectable schmitt-triggered input pe6 keyc 1 input/output input port e6: programmable as input or output key-pressed wake-up input c (with internal pull-up resistor): dynamic pull-up selectable schmitt-triggered input pe7 keyd 1 input/output input port e7: programmable as input or output key-pressed wake-up input d (with internal pull-up resistor): dynamic pull-up selectable schmitt-triggered input pf0 so sda 1 input/output output input/output port f0: programmable as input or output data transmit pin when the serial bus interface is in sio mode data transmit/receive pin when the se rial bus interface is in i2c mode programmable as a push-pull or open-drain output schmitt-triggered input pf1 si scl 1 input/output input input/output port f1: programmable as input or output data receive pin when the serial bus interface is in sio mode clock input/output pin when the serial bus interface is in i2c mode programmable as a push-pull or open-drain output schmitt-triggered input pf2 sck 1 input/output input/output port f2: programmable as input or output clock input/output pin when the serial bus interface is in sio mode pf3 2dreq 1 input/output input port f3: programmable as input or output dma request 2: asserted by an external input/output device to request dma transfer with dmac2 pf4 2dack 1 input/output output port f4: programmable as input or output dma acknowledge 2: indicates acknowledgem ent for a dma transfer request made with dreq2 pf5 3dreq 1 input/output input port f5: programmable as input or output dma request 3: asserted by an external input/output device to request dma transfer with dmac3 pf6 3dack 1 input/output output port f6: programmable as input or output dma acknowledge 3: indicates acknowledgem ent for a dma transfer request made with dreq3 pf7 tbtin 1 input/output input port f7: programmable as input or output 32-bit time base timer input: count i nput to the 32-bit time base timer pg0 - pg7 tc0in - tc7in 8 input/output input port g: individually programmable as input or output 32-bit timer capture trigger input ph0 - ph7 tcout0 - tcout7 8 input/output output port h: individually programmable as input or output 32-bit timer compare match output pj0 int0 1 input/output input port j0: programm able as input or output interrupt request 0: programmable to be high-level, low-level, rising-edge or falling-edge sensitive schmitt-triggered input TMP1962C10BXBG 2006-02-21 tmp1962-12 table 2.2 pin names and functions (5/6) pin name number of pins type function pj1 busmd 1 input/output input port j1: programm able as input or output external bus mode: multiplexed bus mode is selected if this signal is sampled high on the rising edge of the reset signal. separate bu s mode is selected if this signal is sampled low on the rising edge of the reset signal. the busmd pin should be pulled up or down upon a reset according to the bus mode to be used. pj2 1 input/output input port j2: programm able as input or output single boot mode: single boot mode is selec ted if this signal is sampled low on the rising edge of the reset signal. single boot mode is used to rewrite the contents of on-chip flash memory. normal operation is selected if the signal is sampled high on the rising edge of the reset signal. when per forming normal operation, the boot pin should not be pulled down upon a reset. pj3 1 input/output input port j3: programm able as input or output interleave mode: interleave mode is selec ted if this signal is sampled high on the rising edge of the reset signal. the intl v pin should be pulled up when using interleave mode. otherwise, it should be pulled down. pj4 endian 1 input/output input port j4: programm able as input or output endian mode: big-endian mode is selected if this signal is sampled high on the rising edge of the reset signal. little-endian mode is se lected if this signal is sampled low on the rising edge of the reset signal. pk0 - pk7 key0 - key7 8 input/output input port k: individually programmable as input or output key-pressed wake-up input 0 to 7 (with i nternal pull-up resistor): dynamic pull-up selectable schmitt-triggered input pl0 ta4in 1 input/output input port l0: programmable as input or output 8-bit timer 4 input: input to 8-bit timer 4 pl1 ta6in 1 input/output input port l1: programmable as input or output 8-bit timer 6 input: input to 8-bit timer 6 pl2 ta8in 1 input/output input port l2: programmable as input or output 8-bit timer 8 input: input to 8-bit timer 8 pl3 taain 1 input/output input port l3: programmable as input or output 8-bit timer a input: input to 8-bit timer a pl4 tb0in0 1 input/output input port l4: programmable as input or output 16-bit timer 0 input 0: count/capture trigger input to 16-bit timer 0 pl5 tb0in1 1 input/output input port l5: programmable as input or output 16-bit timer 0 input 1: capture trigger input to 16-bit timer 0 pl6 tb1in0 1 input/output input port l6: programmable as input or output 16-bit timer 1 input 0: count/capture trigger input to 16-bit timer 1 pl7 tb1in1 1 input/output input port l7: programmable as input or output 16-bit timer 1 input 1: capture trigger input to 16-bit timer 1 pm0 - pm7 8 input/output port m: individua lly programmable as input or output pn0 txd6 1 input/output output port n0: programmable as input or output serial transmit data 6: programmabl e as a push-pull or open-drain output pn1 rxd6 1 input/output input port n1: programmable as input or output serial receive data 6 pn2 sclk6 6cts 1 input/output input input port n2: programmable as input or output serial clock input/output 6 serial clear-to-send 6: programmabl e as a push-pull or open-drain output pn3 - pn7 5 input/output port n3 to n7: individually programmable as input or output po0 - po7 8 input/output port o: individually programmable as input or output pp0 - pp7 8 input/output port p: individually programmable as input or output TMP1962C10BXBG 2006-02-21 tmp1962-13 table 2.2 pin names and functions (6/6) pin name number of pins type function nmi 1 input nonmaskable interrupt request: caus es an nmi interrupt on the falling edge schmitt-triggered input plloff 1 input this pin should be tied to logic 1 when the frequency multiplied clock from the pll is used; otherwise, it should be tied to l ogic 0 (schmitt-triggered input). rstpup 1 input pull-up resistors for ports 3 and 4 ar e enabled if this signal is sampled high upon a reset; otherwise, the pull-up resistors are disabled. schmitt-triggered input reset 1 input reset (with internal pull-up resi stor): initializes the whole tmp1962. schmitt-triggered input x1/x2 2 input/output connection pins for a high-speed resonator dreset 1 input debug reset: signal for a dsu-ice (schmitt-triggered input with internal pull-up resistor) dclk 1 output debug clock: signal for a dsu-ice dbge 1 input debug enable: signal for a dsu-ice (schmi tt-triggered input with internal pull-up resistor) pcst3 - 0 4 output pc trace status: signals for a dsu-ice sdi/ dint 1 input serial data input/debug interrupt: signal for a dsu-ice (schmitt-triggered input with internal pull-up resistor) sdao/tpc 1 output serial data address output/target pc: signal for a dsu-ice tck 1 input test clock input: jtag test signal (schmi tt-triggered input with i nternal pull-up resistor) tms 1 input test mode select input: jtag test signal (schmitt-triggered input with internal pull-up resistor) tdi 1 input test data input: jtag test signal (schmi tt-triggered input with i nternal pull-up resistor) tdo 1 output test data output: jtag test signal trst 1 input test reset input: jtag test signal (s chmitt-triggered input with internal pull-down resistor) bw0 - 1 2 input both bw0 and bw1 should be ti ed to logic 1 (schmitt-triggered input). vrefh 1 input input pin for high reference voltage for the a/d converter. this pin should be connected to the avcc pin when the a/d converter is not used. vrefl 1 input input pin for low reference voltage for the a/d converter. this pin should be connected to the avss pin when the a/d converter is not used. avcc31 - 32 2 ? power supply pins for the a/d converter . these pins should always be connected to power supply even when the a/d converter is not used. avss 3 ? ground pin for the a/d converter. this pin should always be connected to ground even when the a/d converter is not used. test5 1 input test pin: this pin should be tied to ground. sysrdy 1 output flash memory access enable cvcc15 1 ? 1.5-v power supply pin for the oscillator cvss 1 ? ground pin (0 v) for the oscillator dvcc15 1 ? 1.5-v power supply pin dvcc2 5 ? 2-v power supply pin dvcc31 - 34 9 ? 3-v power supply pins dvss 9 ? ground pin (0 v) note: pj1, pj2, pj3 and pj4 should be held at the prescribed logic states for one system clock cycle before and after the rising edge of reset, with the reset signal being stable in either logic state. TMP1962C10BXBG 2006-02-21 tmp1962-14 table 2.3 shows the correspondence between pins and power supply pins. table 2.3 pins and corresponding power supply pins power supply power supply pin mask type flash type pin mask type flash type p0 dvcc33 dvcc33 pp dvcc31 dvcc31 p1 dvcc33 dvcc33 x1 cvcc15 cvcc2 p2 dvcc33 dvcc33 x2 cvcc15 cvcc2 p3 dvcc33 dvcc33 reset dvcc2 dvcc21 p4 dvcc33 dvcc33 nmi dvcc2 dvcc21 p5 dvcc33 dvcc33 plloff dvcc2 dvcc21 p6 dvcc33 dvcc33 dreset dvcc2 dvcc21 p7 avcc32 avcc32 dclk dvcc2 dvcc21 p8 avcc32 avcc32 dbge dvcc2 dvcc21 p9 avcc31 avcc31 pcst3 - 0 dvcc2 dvcc21 pa dvcc32 dvcc32 sdi/ dint dvcc2 dvcc21 pb dvcc32 dvcc32 sdao/tpc dvcc2 dvcc21 pc dvcc32 dvcc32 tck dvcc34 dvcc34 pd dvcc32 dvcc32 tms dvcc34 dvcc34 pe dvcc32 dvcc32 tdi dvcc34 dvcc34 pf dvcc32 dvcc32 tdo dvcc34 dvcc34 pg dvcc32 dvcc32 trst dvcc34 dvcc34 ph dvcc32 dvcc32 bw1 - 0 dvcc2 dvcc21 pi dvcc34 dvcc34 rstpup dvcc32 dvcc32 pj dvcc2 dvcc21 g3 dvcc2 fvcc2 pk dvcc34 dvcc34 g18 nc fvcc2 pl dvcc34 dvcc34 k5 nc fvss pm dvcc34 dvcc34 l1 nc fvcc pn dvcc31 dvcc31 l15 nc fvcc2 po dvcc31 dvcc31 m15 nc fvss TMP1962C10BXBG 2006-02-21 tmp1962-15 table 2.4 shows the supply voltage for power supply pins. table 2.4 supply voltage for power supply pins power supply pin supply voltage applied for dvcc15 1.35 v - 1.65 v cvcc15 1.35 v - 1.65 v dvcc2 2.3 v - 3.3 v mask type dvcc21 2.2 v - 2.7 v dvcc22 2.2 v - 2.7 v cvcc2 2.2 v - 2.7 v fvcc2 2.2 v - 2.7 v fvcc3 2.9 v - 3.6 v flash type dvcc31 - 34 1.65 v - 3.3 v avcc31 - 32 2.7 v - 3.3 v mask/flash type note 1: avcc32 avcc31 ? when p7 to p9 are used as a/d converter inputs: 2.7 v < avcc3 * ? when p9 (powered by avcc31) is used as an a/d converter input while p7 and p8 (powered by avcc32) are used as ports: 2.7 v avcc31 3.3 v 1.65 v avcc32 avcc31 ? when p7 (powered by avcc32) is used as an a/d converter input while p8 (powered by avcc32) and p9 (powered by avcc31) are used as ports: 2.7 v avcc32 avcc31 3.3 v note 2: with power supplies for cpu and internal logic (mask type: dvcc15/dvcc2/cvcc15, and flash type: dvcc21/dvcc22/cvcc2/fvcc2/fvcc3) being applied, power supplies for other i/o ports can be interrupted on tmp1962. however, when avcc31 for analog power supply is interrupted, overlap current is generated on the tmp1962f10axbg with on-chip flash memory during the transition to be stable in 0 v. overlap current can be suppressed by ad conversion of the conversion result 0 v before interrupting avcc31 power supply, but please suppress it on devices. TMP1962C10BXBG 2006-02-21 tmp1962-16 3. core processor the tmp1962 contains a high-performance 32-bit core processor called the tx19. for a detailed description of the core processor, refer to the tx19 family architecture manual. functions unique to the tmp1962, which are not covered in the architecture manual, are described below. 3.1 reset operation to reset the tmp1962, reset must be asserted for at least 12 system clock periods after the power supply voltage and the internal high-frequency oscillator have st abilized. this time is typically 2.37 s at 40.5 mhz when the on-chip pll is utilized. after a reset, either the pll-multiplied clock or an external clock is selected, depending on the logic state of the plloff pin. by default, the selected clock is geared down to 1/8 for internal operation. the following occurs as a result of a reset: ? the system control coprocessor (cp0) registers w ithin the tx19 core processor are initialized. for details, refer to the architecture manual. ? the reset exception is taken. program control is tr ansferred to the exception handler at a predefined address. this predefined location is called an exce ption vector, which directly indicates the start of the actual exception handler routine. the reset exception is always vectored to virtual address 0xbfc0_0000 (which is the same as for the nonmaskable interrupt exception). ? all on-chip i/o peripheral registers are initialized. ? all port pins, including those multiplexed with on-chip peripheral functions, are configured as either general-purpose inputs or general-purpose outputs. note: all references to register addresses in the following descriptions assume that the tmp1962 is operating in big-endian mode. we recommend the power on sequence of this device ,firstly turn on a power to core (flash: fvcc=2.5v, mask: dvcc15=1.5v) before other power on in this device. dvcc3(1) z (2) kkk i/o power | adc power dvcc15 (fvcc25) dvcc3(1) dvcc3(2) TMP1962C10BXBG 2006-02-21 tmp1962-17 when you use the flash product. when the tmp1962 is powered up, terminating the reset state causes the core processor to wait 30 s before starting operation. this time is required to initiali ze the on-chip flash memory controller. the tmp1962 outputs the sysrdy signal to notify an external device that the core processor ha s started. once the core processor exits from the reset state, the sysrdy signal is driven from low to high. subsequent non-power-up reset operations are controlled with bit 7 (flrmsk) of the flash control/status register (flcs) in the flash memory controller. if the flrmsk bit is cleared to 0 (default), the flash memory controller is always initialized upon a reset. setting the flrmsk bit to 1 prevents the flash memory controller from being initialized upon a reset (data in on-chip flash memory can still be read correctly). in the latter case, the 30 s (t.b.d.) wait time, described above, is not required after a reset so that the core processor starts immediately, driving sysrdy high. the setting of the flrmsk bit is held until the tmp1962 is powered off. usually, flrmsk should be set to 1 as part of initialization after a reset. 7 6 5 4 3 2 1 0 flcs bit symbol flrmsk rdy/bsy (0xffff_e520) read/write w r reset value 0 1 0 function flash reset mask 0: reset the flash memory controller. 1: do not reset the flash memory controller. ready/busy 0: automatic operation in progress 1: automatic operation completed must be written as 0. (the flcs is a 32-bit register.) figure 3.1 flash control/status register the flcs register doesn't exist in the mask rom type an irregular value is read when leading. note 1: the tmp1962 must be powered up with reset asserted. the reset state should not be terminated until after the power supply voltage stabilizes within the valid operating range. note 2: a wait time of at least 500 s is required between the time when the power supply voltages for the stabilize and the time when the reset state is terminated. TMP1962C10BXBG 2006-02-21 tmp1962-18 memory map figure 0.1 shows memory assignment for the tmp1962. figure 0.1 memory map 0xffff_ffff virtual address 16 mbytes reserved kseg1 (uncacheable) kseg2 (cacheable) 16 bytes reserved kseg0 (cacheable) kuseg (cacheable) 0xff00_0000 0xbfcf_ffff 0xbfc0_0000 0xa000_0000 0x8000_0000 0x000f_ffff 0x0000_0000 physical address 16 mbytes reserved kseg2 (1 gbyte) 16 mbytes reserved kuseg (2 gbytes) on-chip rom shadow inaccessible on-chip rom 512 mbytes on-chip peripherals reserved for debugging (2 mb) user program area exception vector area 0xffff_e000 0xffff_6000 (reserved) 0xff3f_ffff 0x400f_ffff 0x4000_0000 0x1fcf_ffff 0x1fc0_0000 0xff20_ffff (reserved) maskable interrupt area 0xff00_0000 0x1fcf_ffff 0x1fc0_0400 0x1fc0_0000 0xffff_dfff 0xfffd_6000 0xfffd_ffff (reserved) on-chip ram ( 32 kb ) shadow on-chip ram ( 40 kb ) note 1: the on-chip 1-mbyte rom is mapped to the addresses from 0x1fc0_0000 through 0x1fcf_ffff and the on-chip 40-kbyte ram is mapped to the addresses from 0xfffd_6000 through 0xfffd_ffff. note 2: the on-chip rom is located in a linear address space beginning at physical address 0x1fc0_0000. all types of exceptions are vectored to the on-chip rom when the bev bit of the system control coprocessor's status register is set to the default value of 1. (when bev = 0, not all exception vectors reside in contiguous locations.) when external memory is used, the bev bit can be cleared to 0. however, using the 32k-byte virtual address range beginning at 0x0000_0000 helps to improve code efficiency, as shown below. the shaded area starting at physical address 0x4000_0000 has a size equal to the on-chip rom size. references to this range (mapped from the virtual address space starting at 0x0000_0000) are rerouted to the on-chip rom. examples: 32-bit isa ? accessing the 0x0000_0000 32-kb region addiu r2, r0, 7 ; r 2 (0x0000_0007) sw r2, io (_t) (r0) ; 0x0000_xxxx (r2) accessed with a single instruction ? accessing other regions lui r3, hi (_f) ; upper 16 bits of address are loaded into r3. addiu r2, r0, 8 ; r 2 (0x0000_0008) sw r2, io (_f) (r3) ; lower 16-bits of address must be added to upper 16 bits. note 3: in the tmp1962, the on-chip 40-kbyte ram is mapped to the addresses from 0xfffd_6000 through 0xfffd_ffff. this area is shadowed to a 32-kbyte address range from 0xffff_6000 through 0xffff_dfff. references to this range are rerouted to the on-chip ram. note 4: the tmp1962 has access to only 16 mbytes of external physical address space. the 16-mbyte physical memory can be located anywhere within the cpu's 3.5-gbyte physical address space through use of programmable chip select signals. however, any address references to the on-chip memory, on-chip peripheral or reserved regions override external memory access. note 5: no instruction should be placed in the last four words of the physical address space. ? if only on-chip rom is used: 0x1fcf_fff0 through 0x1fcf_ffff ? if rom is added off-chip: last four words of the memory installed in the end-user system TMP1962C10BXBG 2006-02-21 tmp1962-19 5. clock/standby control the tmp1962 has the stand-by mode in which the core processor stops to reduce power consumption. figure 5.1 shows the transition between clocking modes. reset instruction normal mode (fc/gear value) interrupt reset released idle mode (cpu halted) (selectable peripheral operation) stop mode (whole chip halted) instruction interrupt transition between clock modes figure 5.1 standby mode flow diagram reset normal mode fc = fpll = fosc 3 fsys = fc/8 fsys = 3fosc/8 fperiph = fgear = fsys reset released plloff = 1 pll used figure 5.2 default clock fr equencies in normal mode fosc: clock frequency supplied via the x1 and x2 pins fpll: pll multiplied clock frequency (x3) fc: clock frequency selected by the plloff pin fgear: clock frequency selected by the gear[1:0] bits in the clock generator?s system control register (syscr1) fsys: system clock frequency the cpu, rom, ram, dmac and intc operate based on this system clock. on-chip peripherals operate on fsys/2. fperiph: clock frequency selected by the fpsel bit in the syscr1 (clock source for the prescalers inside on-chip peripherals) TMP1962C10BXBG 2006-02-21 tmp1962-20 5.1 clock generation 5.1.1 main system clock ? a crystal can be connected between x1 and x2, or x1 can be externally driven with a clock. ? the on-chip pll can be enabled or disabled (bypassed) during reset by using the plloff pin. when the pll is enabled, the input clock frequency is multiplied by three. ? the clock gear can be programmed to divide the clock by 2, 4 or 8. (the default is 1/8 on reset.) ? input clock frequency input frequency range maximum operating frequency minimum operating frequency pll on (for both crystal and external clock) 10 to 13.5 (mhz) 40.5 mhz 3.75 mhz TMP1962C10BXBG 2006-02-21 tmp1962-21 5.1.2 clock source block diagram fosc fc fpll = fosch 3 on-chip peripherals (prescaler input): tmra/b/c, sio, sbi, on-chip peripherals: adc,tmra/b/c, sio, sbi, wdt, port fsys high- speed oscillator x1 x2 syscr0 TMP1962C10BXBG 2006-02-21 tmp1962-22 5.2 clock generator (cg) registers 5.2.1 system clock control registers 31 30 29 28 27 26 25 24 syscr3 bit symbol scosel1 scosel0 alesel lupfg luptm (0xffff_ee00) read/write r/w r r/w reset value 0 0 1 1 1 1 0 0 function scout output select 00: fs 01: fsys/2 10: fsys 11 : (reserved) ale output width select 0: fsys 0.5 1: fsys 1.5 must be written as 0 (flash type) must be written as 0 (flash type) pll lock 0: locked 1: unlocked pll lock time select 0: 2 16 /input frequency 1: 2 12 /input frequency 23 22 21 20 19 18 17 16 syscr2 bit symbol drvosch wupt1 wupt0 stby1 stby0 drve (0xffff_ee01) read/write r/w r/w r/w reset value 0 0 1 0 1 1 0 0 function high- speed oscillator drive capability 0: high 1: low must be written as 0 (flash type) oscillator warm-up time (note 2) 00: no warm-up 01: 2 8 /input frequency 10: 2 14 /input frequency 11: 2 16 /input frequency standby mode select (note 1) 00: reserved 01: stop mode 10: reserved 11: idle mode 0: pins are not driven in stop mode. 1: pins are driven in stop mode. (see table 3.3.9.) 15 14 13 12 11 10 9 8 syscr1 bit symbol fpsel gear1 gear0 (0xffff_ee02) read/write r/w r/w reset value 0 0 0 0 0 0 1 1 function must be written as 0 (flash type) fperiph select 0: fgear 1: fc must be written as 0 (flash type) high-speed clock (fc) gear select 00: fc 01: fc/2 10: fc/4 11: fc/8 7 6 5 4 3 2 1 0 syscr0 bit symbol prck1 prck0 (0xffff_ee03) read/write r/w reset value 1 0 1 0 0 0 0 0 function must be written as 1 (flash type) must be written as 0 (flash type) must be written as 1 (flash type) must be written as 0 (flash type) must be written as 0 prescaler clock select 00: fperiph/16 01: fperiph/8 10: fperiph/4 11: (reserved) note 1: the config register in the cp0 has the doze and halt bits. setting the halt bit puts the tmp1962 in one of the standby modes, as specified by the stby[1:0] bits in the syscr2. setting the doze bit puts the tmp1962 in idle mode, irrespective of the settings of the stby[1:0] bits. note 2: the wupt[1:0] bits in the syscr2 must not be ch anged during the oscillator warm-u p period. the luptm bit in the syscr3 must not be changed during the pll lock period. note 3: the oscillator warm-up period (wup) timer is also used as the pll lock timer. note 4: when the pll is used, the wupt[1:0] bits in the syscr2 must not be set to 00 (no warm-up). note 5: when the pll is not used, the lupfg bit in the syscr3 is always read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-23 5.2.2 stop wake-up interrupt control registers (intcg registers) 31 30 29 28 27 26 25 24 imcga0 bit symbol emcg31 emcg30 int3en (0xffff_ee10) read/write r/w r/w reset value 1 0 0 function wake-up int3 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int3 enable 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcg21 emcg20 int2en read/write r/w r/w reset value 1 0 0 function wake-up int2 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int2 enable 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg11 emcg10 int1en read/write r/w r/w reset value 1 0 0 function wake-up int1 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int1 enable 0: disable 1: enable 7 6 5 4 3 2 1 0 bit symbol emcg01 emcg00 int0en read/write r/w r/w reset value 1 0 0 function wake-up int0 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int0 enable 0: disable 1: enable TMP1962C10BXBG 2006-02-21 tmp1962-24 31 30 29 28 27 26 25 24 imcgb0 bit symbol (0xffff_ee14) read/write r/w r/w reset value 1 1 0 function . must be written as 0. 23 22 21 20 19 18 17 16 bit symbol read/write r/w r/w reset value 1 0 0 function must be written as 0. 15 14 13 12 11 10 9 8 bit symbol emcg51 emcg50 kwupen read/write r/w r/w reset value 0 1 0 function wake-up kwup sensitivity 00: setting prohibited 01: high level 10: setting prohibited 11: setting prohibited these bits must be set to 01. kwup enable 0: disable 1: enable 7 6 5 4 3 2 1 0 bit symbol emcg41 emcg40 int4en read/write r/w r/w reset value 1 0 0 function wake-up int4 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int4 enable 0: disable 1: enable TMP1962C10BXBG 2006-02-21 tmp1962-25 31 30 29 28 27 26 25 24 imcgc0 bit symbol emcgb1 emcgb0 int6en (0xffff_ee18) read/write r/w r/w reset value 1 0 0 function wake-up int6 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge i n t 6 enable 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcga1 emcga0 int5en read/write r/w r/w reset value 1 0 0 function wake-up int5 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int5 enable 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol read/write r/w r/w reset value 1 1 0 function must be written as 0. 7 6 5 4 3 2 1 0 bit symbol read/write r/w r/w reset value 1 1 0 function must be written as 0. TMP1962C10BXBG 2006-02-21 tmp1962-26 31 30 29 28 27 26 25 24 imcgd0 bit symbol emcgf1 emcgf0 intaen (0xffff_ee1c) read/write r/w r/w reset value 1 0 0 function wake-up inta sensitivity 00: low level 01: high level 10: falling edge 11: rising edge inta enable 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcge1 emcge0 int9en read/write r/w r/w reset value 1 0 0 function wake-up int9 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int9 enable 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcgd1 emcgd0 int8en read/write r/w r/w reset value 1 0 0 function wake-up int8 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int8 enable 0: disable 1: enable 7 6 5 4 3 2 1 0 bit symbol emcgc1 emcgc0 int7en read/write r/w r/w reset value 1 0 0 function wake-up int7 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int7 enable 0: disable 1: enable TMP1962C10BXBG 2006-02-21 tmp1962-27 note 1: the edge/level sensitivity must be defined for an interrupt pin which is enabled as wake-up signaling to exit stop mode. note 2: interrupt programming must follow these steps: 1. configure the pin as an interrupt input, if the pin is multiplexed with a general-purpose port. 2. set the active state for the interrupt during initialization. 3. clear any interrupt request. 4. enable the interrupt. note 3: the above steps must be performed with the relevant interrupt pin disabled. note 4: the tmp1962 has 15 interrupt sources which can be used for wake-up signaling to exit stop mode: int0 to inta, intrtc, inttb2, inttb3 and kwup0 to kwupd. when one of int0 to inta is used for stop wake-up signaling, it must be enabled as a wake-up interrupt source in the cg block and its interrupt sensitivity must be specified in the cg block. when one of kwup0 to kw upd is used for stop wake-up signaling, it must be enabled as a wake-up interrupt source in the cg block and its interrupt sensitivity must be specified in the kwupstx. in the intc block, the sensitivity for all of the above 15 interrupt sources must be set to the high level. example: enabling the int0 interrupt imcga0 TMP1962C10BXBG 2006-02-21 tmp1962-28 5.2.3 exit stop mode interrupt clear request register (eicrcg register) 31 30 29 28 27 26 25 24 eicrcg bit symbol (0xffff_ee20) read/write reset value function 23 22 21 20 bit symbol read/write reset value function 15 14 13 12 bit symbol read/write reset value function 7 6 5 4 3 2 1 0 bit symbol icrcg3 icrcg2 icrcg1 icrcg0 read/write w reset value ? ? ? ? function clear interrupt request 0000: int0 0101: kwup 1010: int5 0001: int1 0110: reserved 1011: int6 0010: int2 0111: reserved 1100: int7 0011: int3 1000: reserved 1101: int8 0100: int4 1001: reserved 1110: int9 1111: inta note 6: interrupt requests for the above 15 interrupt s ources which can be used for wake-up signaling to exit stop mode are cleared as follows: 1. the clearing of kwup interrupt sources is controlled through the kwupclr register. 2. clearing the int0 to inta, inttb2, inttb3 and intrtc interrupt requests requires two register settings: first, the eicrcg register in the cg block, an d then the intclr register in the intc block. 3. the clearing of other interrupt sources is controlled through the intclr register alone. TMP1962C10BXBG 2006-02-21 tmp1962-29 5.3 system clock control section a system reset initializes the syscr0.xen b it to 1, the syscr0.xten bit to 0 and the syscr1.gear[1:0] bits to 11, putting the tmp1962 in single-clock mode. if the on-chip pll is enabled, the pll reference clock is always multiplied by three. by default, the system clock frequency (fsys) is geared down to fc/8, where fc = fosc x 3 (fosc is the oscillator frequency). for example, if a 13.5-mhz crystal is connected between the x1 and x2 pins, the fsys clock operates at 5.0625 mhz (13.5 x 3 x 1/8). 5.3.1 oscillation stabilization time when a crystal is connected between the x1 and x2 pins and/or xt1 and xt2 pins, the integrated warm-up period timer is used to assure oscillation stability. the warm-up period can be selected through the [wupt1:0] bits of the sys cr2 to suit the crystal used. table 5.1 shows the warm-up periods required when the clocking is switched between normal and slow modes. table 5.1 warm-up periods warm-up period select syscr2.wupt[1:0] high-speed clock (fosc) 01 (2 8 /oscillation frequency) 19.0 ( s) 10 (2 14 /oscillation frequency) 1.214 (ms) 11 (2 16 /oscillation frequency) 4.855 (ms) assumption: fosc = 13.5 mhz note: the system clock frequency must be initialized to 3.75 mhz or higher. note 1: no warm-up is necessary when the tmp1962 is driven by an external oscillator clock which is already stable. note 2: because the warm-up period timer is clocked by the oscillator clock, any frequency fluctuations will lead to small timer errors. table 5.1 should be considered as approximate values. TMP1962C10BXBG 2006-02-21 tmp1962-30 5.3.2 system clock output the fsys, fsys/2 or fs clock can be driven out from the p44/scout pin. the p44/scout pin is configured as scout (system clock output) by programming the port 4 registers as follows: p4cr.p44c = 1 and p4fc.p44f = 1. the output clock is selected through the syscr3.scosel[1:0] bits. table 5.2 shows the pin states in each clocking mode when the p44/scout pin is configured as scout. table 5.2 scout output states standby modes mode scout select normal, slow idle stop TMP1962C10BXBG 2006-02-21 tmp1962-31 5.4 prescaler clock control section the tmra01 to tmraab, tmrb0 to tmrb3, tmrc, sio0 to sio6 and sbi have a clock prescaler. the prescaler clock source ( t0) can be selected from fperiph/16, fperiph/8 and fperiph/4 through the prck[1:0] bits of the syscr0. fperiph can be se lected from either fgear or fc through the fpsel bit of the syscr1. the default reset values select fgear as fperiph, and fperiph/16 as t0. 5.5 clock frequency multip lication section (pll) the on-chip pll multiplies the frequency of the high-speed oscillator clock (fosc) by three to generate the fpll clock. to use the pll, the plloff pi n must be high when reset is released. being an analog circuit, the pll re quires a certain duration of time (called lock time) to stabilize, like an oscillator. the oscillator warm-up period (wup) timer is also used as the pll lock timer. the luptm bit in the syscr3 must be programmed so that the following relationship is satisfied: pll lock time oscillator warm-up time at reset, the default lock-up time is 2 16 /input frequency. setting the wup timer control bit (syscr0.wuef) star ts the pll lock timer. the syscr3.luptm bit remains set while the pll is out of lock, and is cleared when the pll locks. in real-time applications whose soft ware execution time is critical, once the pll has gone out of lock in a standby mode, software must determine before resuming operation whether the pll has locked (after the oscillator warm-up time has expired) in order to assure clock stability. note 1: if the plloff pin is low when reset is released, the pll will be disabled and the oscillator clock will be driven with no frequency multiplication. note 2: the following must be noted when changing the clock gear value. the clock gear can be changed by the programming of the gear[1:0] bits of the syscr1. it takes a few clock cycles for a gear change to take effect. therefore, one or more instructions following the instruction that changed the clock gear value may be executed using the old clock gear value. if subsequent instructions need to be executed with a new clock gear value, a dummy instruction (one that executes a write cycle) should be inserted after the instruction that modifies the clock gear value. when the clock gear is used, the prescalers within on-chip peripherals must be programmed so that the prescaler output ( tn) satisfies the following relationship: tn < fsys/2 the clock gear must not be changed while a time r/counter or other peripherals are operating. TMP1962C10BXBG 2006-02-21 tmp1962-32 5.6 standby control section the tmp1962 provides support for several levels of power reduction. while in normal mode, setting the halt bit of the config register within the tx19 core pr ocessor causes the tmp1962 to enter one of the standby modes ? idle, stop ? as specified by the syscr2.stby[1:0] bits. setting the doze bit of the config register causes the tmp1962 to enter idle (doze) m ode, irrespective of the setting of syscr2.stby[1:0]. the characteristics of the idle, stop modes are as follows: idle: the cpu stops. on-chip peripherals can be selectively enabled and disabled through use of a register bit in a given peripheral, as shown in table 5.3. if an on-chip peripheral has its register bit cleared to disable operation in idle mode, it stops when the tm p1962 enters idle mode, holding the state in which it is placed when it stops. table 5.3 idle mode register settings peripheral idle mode bit tmra01 to ab taxxrun TMP1962C10BXBG 2006-02-21 tmp1962-33 5.6.1 tmp1962 operation in normal and standby modes table 5.4 tmp1962 operation in normal and standby modes operating mode operating states normal the tx19 core processor and on-chip peripherals operate at frequencies specified in the cg block. idle (halt) the processor and dmac operations stop; other on-chip peripherals can be selectively disabled. idle (doze) processor operation stops; the dmac is operational; other on-chip peripherals can be selectively disabled. stop all processor and peripheral operations stop completely. 5.6.2 cg operation in normal and standby modes table 5.5 cg states in normal and standby modes clock source mode oscillator pll clock supply to peripherals clock supply to cpu crystal normal idle (halt) selectable idle (doze) selectable stop external clock normal idle (halt) selectable idle (doze) selectable stop : operational, or clock supplied . stopped, or clock not supplied TMP1962C10BXBG 2006-02-21 tmp1962-34 5.6.3 processor and peripheral block operation in standby modes table 5.6 processor and peripheral blocks in standby modes circuit block clock source idle (doze) idle (halt) stop tx19 core processor dmac intc external bus interface external bus mastership i/o ports adc sio i 2 c tmra tmrb tmrc wdt 2-phase pulse input counter fsys selectable on a block-by-block basis cg ? : on : off 5.6.4 wake-up signaling there are two ways to exit a standby mode: an interrupt request or a reset signal. availability of wakeup signaling depends on the settings of the interrupt mask level bits, cmask[15:13], of the cp0 status register and the cu rrent standby mode (see table 5.7). ? wake-up via interrupt signaling the operation upon return from a standby mode varies, depending on the interrupt priority level programmed before entering a standby mode. if the interrupt priority level is greater than or equal to the processor?s interrupt mask level, execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated the standby mode (i.e., the instruction that set the halt or doze bit in the conf ig register). if the interrupt priority level is less than the processor?s interrupt mask level, program execution resumes with the instruction that activated the standby mode. the interrupt is left pending. nonmaskable interrupts are always serviced upon return from a standby mode, regardless of the current interrupt mask level. ? wake-up via reset signaling reset signaling always brings the tmp1962 out of any standby mode. a wake-up from stop mode must, however, allow sufficient time for the oscillator to restart and stabilize (see table 5.1). a reset does not affect the contents of the on-chip ram, but initializes everything else, whereas an interrupt preserves all internal states that were in effect before the standby mode was entered. TMP1962C10BXBG 2006-02-21 tmp1962-35 for details of stop wake-up interrupts and other normal interrupts, refer to chapter 6, ?interrupts.? table 5.7 wake-up signaling sources and wake-up operations interrupt masking unmasked interrupt (request_level > mask_level) masked interrupt (request_level mask_level) standby mode idle (programmable) stop idle (programmable) stop nmi ? ? (note 1) ? ? (note 1) intwdt ? ? int0 to a kwup0 to d ? ? ? (note 1) ? (note 1) (note 1) (note 1) inttb0 to 3 ? intta0 to d ? interrupts intrx0 to 6, tx0 to 6 ints intad/adhp/adm ? ? ? wake-up signaling sources reset ? ? ? ? ? : execution resumes with the interrupt service routine. (reset initializes the whole tmp1962.) : execution resumes with the instruction that activa ted the standby mode. the interrupt is left pending. : cannot be used to exit a standby mode. note 1: the tmp1962 exits the stanby mode after the warm-up period timer expires. note 2: if the interrupt request level is greater than the mask level, an interrupt signal which is programmed as level-sensitive must be held active until interrupt processing begins. otherwise, the interrupt will not be serviced successfully. note 3: if interrupts are disabled in the cpu, all interrup ts other than those used for wake-up signaling must also be disabled in the interrupt controller (intc) before a stanby mode is entered. otherwise, any interrupt could take the tmp1962 out of the stanby mode. TMP1962C10BXBG 2006-02-21 tmp1962-36 5.6.5 stop mode the stop mode stops the whole tmp1962, including the on-chip oscillator. pin states in stop mode depend on the setting of the sys cr2.drve bit, as shown in table 5.8. upon detection of wake-up signaling, the warm-up period timer should be activated to allow sufficient time for the oscillator to restart and stabilize before exiting stop mode. after that, the system clock output can restart. on exiting stop mode, the tmp1962 starts operation in the mode (normal or slow) in which it was in before entering stop mode. applicable register bits must be programmed prior to the instruction that activ ates a standby mode. the warm-up period is chosen through the syscr2.wupt[1:0] bits. 5.6.6 returning from stop mode (1) mode transitions from normal to stop to normal when fosc = 13.5 mhz w-up time select syscr2.wupt[1:0] w-up time (fosc) 01 (2 8 /fosc) setting prohibited 10 (2 14 /fosc) 1.214 ms 11 (2 16 /fosc) 4.855 ms note: in the tmp1962f10axb, the syscr2.wupt[1:0] bits (war m-up time) must not be set to 00 or 01 when the mode is changed from normal to stop, because this does not allow enough time (at least 150 s) for the internal system to resume when the tmp1962 exits stop mode. note: the wupt[1:0] bits must not be set to 01 because this does not allow enough time for the internal system to resume. normal normal stop fsys (high-speed clock) mode cg (high-speed clock) warm-up (w-up) high-speed clock oscillator started warm-up started warm-up completed system clock stopped TMP1962C10BXBG 2006-02-21 tmp1962-37 table 5.8 pin states in stop mode (1/2) pins input/output syscr2. drve = 0 syscr2. drve = 1 p00 to p07 input mode output mode ad0 to ad7, d0 to d7 ? ? ? ? output ? p10 to p17 input mode output mode, a8 to a15 ad8 to ad15, d8 to d15 ? ? ? ? output ? p20 to p27 input mode output mode, a0 to a7/a16 to a23 ? ? ? output p30 (/rd), p31 (/wr) output pin ? output p32 to p36 input mode output mode pu * pu * input output p37 (ale) input mode output mode ale (output mode) ? ? output low input output output low p40 to p43 input mode output mode pu * pu * input output p44 (scout) input mode output mode ? ? input output p50 to p57 input mode output mode, a0 to a7 ? ? ? output p60 to p67 input mode output mode, a8 to a15 ? ? ? output p7, p8, p9 input pin ? ? pa0 to pa7 input mode output mode ? ? input output pb0, pb1, pb4, pb7 input mode output mode ? ? input output pb2, pb3, pb5, pb6 input mode output mode int5 to int8 (input mode) ? ? input input output input pc0 to pc7 input mode output mode ? ? input output pd0 to pd6 input mode output mode ? ? input output pd7 input mode output mode key8 (input mode) ? ? input input output input pe0 to pe2 input mode output mode ? ? input output pe3 to pe7 input mode output mode key9 to keyd (input mode) ? ? input input output input pf, pg, ph, pi0, pi7 input mode output mode ? ? input output pi1 to pi6 input mode output mode int1 to 4,int9,inta (input mode) ? ? input input output input pj0 input mode output mode int0 (input mode) ? ? input input output input pj1 to pj4 input mode output mode ? ? input output pk0 to pk7 input mode output mode key0 to key7 (input mode) ? ? input input output input TMP1962C10BXBG 2006-02-21 tmp1962-38 table 5.8 pin states in stop mode (2/2) pins input/output syscr2. drve = 0 syscr2. drve = 1 pl, pm, pn, po, pp input mode output mode ? ? input output nmi input pin input input reset input pin input input bm0, bm1 input pin input input plloff input pin input input rstpup input pin input input sysrdy output pin output high output high x1 input pin ? ? x2 output pin output high output high ? : pins configured for input mode and input-only pins are disabled. pi ns configured for output mode and output-only pins assume the high-impedance state. input: the input gate is active; the input voltage must be hel d at either the high or low level to keep the input pin from floating. output: pin direction is output. pu * : programmable pull-up. because the input gate is al ways disabled, no overlap current flows while in high-impedance state. TMP1962C10BXBG 2006-02-21 tmp1962-39 6. interrupts interrupt processing is coordinated between the cp0 status register, the interrupt controller (intc) and the clock generator (cg). the status register contains the interrupt mask level field (cmask[15:13]) and the interrupt enable bit (iec). for interrupt processing, also refer to chapter 9, "exception handling" in the tx19 architecture manual. the tmp1962 interrupt mechanism includes the following features: ? 4 cpu internal interrupts (software interrupts) ? 26 external interrupt pins ( nmi , int0-inta, kwup0-kwupd) ? 56 on-chip peripheral interrupts (including a wdt interrupt) ? vector generation for each interrupt source ? programmable priority for each interrupt source (7 levels) ? dma trigger on interrupt TMP1962C10BXBG 2006-02-21 tmp1962-40 figure 6.1 general interrupt mechanism note: there are interrupt enable and polarity bits in these registers: 1. interrupt mode control registers (imcxx) in the intc 2. imcgxx registers in the cg 3. kwup status registers (kwupstx) in the kwup intnen standby wakeup control 12 interrupt detection block high/low level/edge select high level 12 active high level 12 kwup int0 - inta 11 key0 - keyd 1 cg other interrupts intc core status register 12 active high level high/low level/edge select input enable/disable for each interrupt source kwup imcxx register imcgxx register kwupst0 - d register TMP1962C10BXBG 2006-02-21 tmp1962-41 (1) external interrupts int0-int4, kwup0-kwupd, in trtc, inttb2 and inttb3 (2-phase pulse input counter) 1) int0-inta ? when enabled for stop wake-up signaling ? the emcgxx field in the cg's imcgxx register de fines the interrupt polarity. (refer to section 5.2.2, "intcg registers.") ? the intxen bit in the cg's imcgxx register controls whether these interrupt sources are enabled as wake-up signal sources (1 = enable). (refer to section 5.2.2, "intcg registers.") ? if enabled, the interrupt polarity (eimxx) field in the intc's imcxx register has no effect, but must be set to 01, or high level. (refer to section 6.4, "intc registers.") ? when disabled for stop wake-up signaling ? the interrupt polarity (eimxx) field in the intc's imcxx register defines the interrupt polarity. (refer to section 6.4, "intc registers.") 2) kwup0-kwupd ? when enabled for stop wake-up signaling ? the emcg5[1:0] field in the cg's imcgb0 register has no effect, but must be set to 01, or high level. (refer to section 5.2.2, "intcg registers.") ? the kwupen bit in the cg's imcgb0 register cont rols whether these interrupt sources are enabled as wake-up signal sources (1 = enable). (ref er to section 5.2.2, "intcg registers.") ? the interrupt polarity (eim6[1:0]) field in the intc's imc1 register has no effect, but must be set to 01, or high level. (refer to section 6.4, "intc registers.") ? for each of these interrupt sources, the kwupstx register in the kwup block defines the interrupt polarity and controls whether interrupts are enabled. ? when disabled for stop wake-up signaling ? the interrupt polarity (eim6[1:0]) field in the intc's imc1 register has no effect, but must be set to 01, or high level. (refer to section 6.4, "intc registers.") ? for each of these interrupt sources, the kwupstx register in the kwup block defines the interrupt polarity and controls whether interrupts are enabled. TMP1962C10BXBG 2006-02-21 tmp1962-42 (2) internal interrupts (except intrtc and in ttb2/inttb3 in 2-phase pulse count mode) these interrupts are progra mmable through the intc. the intc collects interrupt events, prioritizes them a nd presents the highest-prio rity request to the tx19 core processor. interrupt programming interrupt sensing int0 ? inta imcgx reg.in cg imcx reg.in intc when enabled for stop wake-up signaling, the polarity field in the intc has no effect, but must always be set to "high-level." the actual sensitivity is progr ammed in the cg. when disabled for stop wake-up signaling, interrupt sensitivity is programmed in the intc. in either case, each i nterrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. kwup0 ? kwupd imcgx reg.in cg imcx reg.in intc kwupstn the polarity field in the intc has no effect, but must always be set to "high-level." when enabled for stop wake-up signaling, the polarity field in the cg has no effect, but must always be set to "high-level." the actual sensitivity is programmed in the kwupnst. when disabled for stop wake-up signaling, the cg need not be programmed. in either cas e, each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. intdman imcx reg.in intc falling edge on-chip peripherals others imcx reg.in intc rising edge ? example register settings here are example register settings required to enable and disable the int0 inte rrupt as a source of the stop wake-up signal (negative-edge triggered). a. enabling the interrupt imcga0 TMP1962C10BXBG 2006-02-21 tmp1962-43 6.1 interrupt sources the tmp1962 provides a reset interrupt, nonmaskable interrupts, and maskable interrupts: (1) reset and nonmaskable interrupts the reset pin causes a reset interrupt. the nmi pin functions as a nonmaskable interrupt. the on-chip watchdog timer (wdt) is also capable of being a source of a nonmaskable interrupt (intwdt). reset and nonmaskable interrupts are always vectored to virtual address 0xbfc0_0000. (2) maskable interrupts the tmp1962 supports two types of maskable interr upts: software and hardware interrupts. maskable interrupts are vectored to virtual addresses 0xbfc0_0210 through 0xbfc0_0260, as shown below. interrupt source virtual vector address reset nonmaskable 0xbfc0_0000 software swi0 0xbfc0_0210 swi1 0xbfc0_0220 swi2 0xbfc0_0230 swi3 0xbfc0_0240 maskable hardware 0xbfc0_0260 note 1: the above table shows the vector addresses when the b ev bit in the cp0 status register is set to 1. when bev = 1, all exception vectors reside in the on-chip rom space. note 2: software interrupts are posted by setting one of the sw[3:0] bits in the cp0 cause register. software interrupts are distinct from the "software set" interrupt which is one of the hardware interrupt sources. a software set interrupt is posted from the intc to the tx19 core processo r when the il0[2:0] field in the intc's imc0 register is set to a non-zero value. TMP1962C10BXBG 2006-02-21 tmp1962-44 table 6.1 hardware interrupt sources interrupt number ivr[9 : 0] interrupt source interrupt control register address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 000 010 020 030 040 050 060 070 080 090 0a0 0b0 0c0 0d0 0e0 0f0 100 110 120 130 140 150 160 170 180 190 1a0 1b0 1c0 1d0 1e0 1f0 200 210 220 230 240 250 260 270 280 290 2a0 2b0 2c0 2d0 2e0 2f0 300 310 320 330 340 350 360 370 380 390 3a0 3b0 3c0 3d0 3e0 3f0 software set int0 pin int1 pin int2 pin int3 pin int4 pin kwup reserved intrx6: sio receive (channel.6) inttx6: sio transmit (channel.6) int5 pin int6 pin int7 pin int8 pin int9 pin inta pin intrx0: sio receive (channel.0) inttx0: sio transmit (channel.0) intrx1: sio receive (channel.1) inttx1: sio transmit (channel.1) ints0: serial bus interface 0 intrx2: sio receive (channel.2) inttx2: sio transmit (channel.2) intadhp: high-priority a/d conversion complete intadm: a/d conversion monitoring inttag0: 8-bit timer group 0 inttag1: 8-bit timer group 1 inttag2: 8-bit timer group 2 reserved inttb0: 16-bit timer 0 inttb1: 16-bit timer 1 intrx3: sio receive (channel.3) inttx3: sio transmit (channel.3) intrx4: sio receive (channel.4) inttx4: sio transmit (channel.4) intrx5: sio receive (channel.5) inttx5: sio transmit (channel.5) reserved reserved reserved intcapg0: input capture group 0 intcapg1: input capture group 1 reserved intcmp0: compare 0 intcmp1: compare 1 intcmp2: compare 2 intcmp3: compare 3 intcmp4: compare 4 intcmp5: compare 5 inttb2: 16-bit timer 2 inttb3: 16-bit timer 3 intcmp6: compare 6 intcmp7: compare 7 reserved intdma0: dma complete (channel 0) intdma1: dma complete (channel 1) intdma2: dma complete (channel 2) intdma3: dma complete (channel 3) reserved intad: a/d conversion complete intdma4: dma complete (channel 4) intdma5: dma complete (channel 5) intdma6: dma complete (channel 6) intdma7: dma complete (channel 7) imc0 imc1 imc2 imc3 imc4 imc5 imc6 imc7 imc8 imc9 imca imcb imcc imcd imce imcf 0xffff_e000 0xffff_e004 0xffff_e008 0xf fff_e00c 0xffff_e010 0xffff_e014 0xffff_e018 0xffff_e01c 0xffff_e020 0xffff_e024 0xffff_e028 0xffff_e02c 0xffff_e030 0xffff_e034 0xffff_e038 0xffff_e03c TMP1962C10BXBG 2006-02-21 tmp1962-45 6.2 interrupt detection when enabled as a stop wake-up signal, the pola rities of int0-int4 are programmed in the emcgxx field of the imcgxx register within the cg; in this case, the eimxx field of the imcx register within the intc has no effect; however, it must be set to "high-le vel sensitive". for each of kwup0-kwupd, the kwupstn register within the kwup block defines the interrupt pol arity and controls whether in terrupts are enabled. the emcg field of the imcgb register w ithin the cg and the eimxx field of the imcx register within the intc have no effect; however, they must be set to "high-level sensitive". the polarity of intrtc must be configured as "rising-edge triggered" in the emcgxx field of the imcgxx re gister within the cg; in this case, the eimxx field of the imcx register within the intc has no effect; however, it must be set to "high-level sensitive". all other interrupts are always programmed in the emcgxx field of the intc?s imcx register. each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. when a selected transition is detected, an interrupt request is issued to the intc (except for the nmi and intwdt interrupts, which ar e directly delivered to the tx19 core processor). when the above interrupts are disabled for stop wake-up signaling, the cg need not be programmed. when int0-inta are disabled for wake-up signaling, only the intc has to be programmed. when kwup0-kwupd are disabled for wake-up signaling, only the intc and kwupstx have to be programmed. it is the responsibility of software (an interrupt handler routine) to determine the cause of an interrupt and to clear the interrupt condition. int0-inta and intrc re quire software access to two registers: the eicrcg register (icrcg field) in the cg and the intclr register (eiclr field) in the intc. kwup0-kwupd require software access to the kwupclr. other interrupts can be cleared by writing their assigned value to the eiclr field in the intc's intclr register. for an external interrupt configured as level-sensitive, software must explicitly address the device in question and clear the interrupt condition. a level-sensitive interrupt signal must be held active until the tx19 core pr ocessor reads its interrupt vector from the interrupt vector register (ivr). (example register settings required to enable the int0 interrupt as a source of the stop wake-up signal) imcga0 TMP1962C10BXBG 2006-02-21 tmp1962-46 6.3 resolving interrupt priority (1) seven interrupt priority levels the interrupt mode control registers (imcx) contain a 3-bit interrupt priority level (ilx[2:0]) field for each interrupt source, which ranges from level 0 to leve l 7, with level 7 being the highest priority. level 0 indicates that the interrupt is disabled. (2) interrupt level notification when an interrupt event occurs, the intc sends its priority level to the tx19 core processor. the processor can determine the priority level of an interrupt being requested by reading the il field in the cp0 cause register. if multiple interrupt events having different priority levels occur simultaneously, the intc sends the highest priority level. (3) interrupt vector (interrupt source notification) whenever an interrupt request is made, the intc automa tically sets its vector in the ivr. the tx19 core processor can determine the exact cause of an interrupt by reading the ivr. if multiple interrupt requests occur at the same level, the interrupt with the smallest interrupt number is deliver ed. when no interrupt is pending, the ivr[9:4] field in the ivr contains a value of zero. when the tx19 core processor responds to a request with an interrupt acknow ledge cycle, the intc forwards the interrupt vector for that interrupt requ est. at this time, the tx19 core processor saves the priority level value in the cmask field of the cp0 status register. TMP1962C10BXBG 2006-02-21 tmp1962-47 6.4 register description table 6.2 intc register map address symbol register name corresponding interrupt number 0xffff_e060 intclr interrupt request clear control register all (63 ? 0) 0xffff_e040 ivr interrupt vector register all (63 ? 0) 0xffff_e03c imcf interrupt mode control register f 63 ? 60 0xffff_e038 imce interrupt mode control register e 59 ? 56 0xffff_e034 imcd interrupt mode control register d 55 ? 52 0xffff_e030 imcc interrupt mode control register c 51 ? 48 0xffff_e02c imcb interrupt mode control register b 47 ? 44 0xffff_e028 imca interrupt mode control register a 43 ? 40 0xffff_e024 imc9 interrupt mode control register 9 39 ? 36 0xffff_e020 imc8 interrupt mode control register 8 35 ? 32 0xffff_e01c imc7 interrupt mode control register 7 31 ? 28 0xffff_e018 imc6 interrupt mode control register 6 27 ? 24 0xffff_e014 imc5 interrupt mode control register 5 23 ? 20 0xffff_e010 imc4 interrupt mode control register 4 19 ? 16 0xffff_e00c imc3 interrupt mode control register 3 15 ? 12 0xffff_e008 imc2 interrupt mode control register 2 11 ? ?8 0xffff_e004 imc1 interrupt mode control register 1 7 ? 4 0xffff_e000 imc0 interrupt mode control register 0 3 ? 0 6.4.1 interrupt vector register (ivr) this register indicates the vector for the inte rrupt source when there is an interrupt event. 31 30 29 28 27 26 25 24 ivr bit symbol (0xffff_e040) read/write r/w reset value 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 b i t s y m b o l read/write r/w reset value 0 0 0 0 0 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol ivr9 ivr8 read/write r/w r reset value 0 0 0 0 0 0 0 0 function interrupt vector for the source of the current interrupt 7 6 5 4 3 2 1 0 bit symbol ivr7 ivr6 ivr5 ivr4 read/write r reset value 0 0 0 0 0 0 0 0 function interrupt vector for the source of the current interrupt TMP1962C10BXBG 2006-02-21 tmp1962-48 6.4.2 interrupt mode control registers these registers control the interrupt priority level, active polarity, either level or edge sensitivity, and dma triggering. 31 30 29 28 27 26 25 24 imc0 bit symbol eim31 eim30 dm3 il32 il31 il30 (0xffff_e000) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 3 as dma trigger when dm3 = 0 interrupt number 3 (int2) priority level 000: interrupt disabled 001-111: 1-7 when dm3 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim21 eim20 dm2 il22 il21 il20 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 2 as dma trigger when dm2 = 0 interrupt number 2 (int1) priority level 000: interrupt disabled 001-111: 1-7 when dm2 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim11 eim10 dm1 il12 il11 il10 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 1 as dma trigger when dm1 = 0 interrupt number 1 (int0) priority level 000: interrupt disabled 001-111: 1-7 when dm1 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim01 eim00 dm0 il02 il01 il00 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: setting prohibited 10: setting prohibited 11: setting prohibited must be set to 00. dma trigger 0: disable 1: enable interrupt number 0 as dma trigger when dm0 = 0 interrupt number 0 (software set) priority level 000: interrupt disabled 001-111: 1-7 when dm0 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-49 31 30 29 28 27 26 25 24 imc1 bit symbol eim71 eim70 dm7 il72 il71 il70 (0xffff_e004) read/write r/w reset value 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 23 22 21 20 19 18 17 16 bit symbol eim61 eim60 dm6 il62 il61 il60 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: high level 10: setting prohibited 11: setting prohibited must be set to 01. dma trigger 0: disable 1: enable interrupt number 6 as dma trigger when dm6 = 0 interrupt number 6 (kwup) priority level 000: interrupt disabled 001-111: 1-7 when dm6 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim51 eim50 dm5 il52 il51 il50 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 5 as dma trigger when dm5 = 0 interrupt number 5 (int4) priority level 000: interrupt disabled 001-111: 1-7 when dm5 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim41 eim40 dm4 il42 il41 il40 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 4 as dma trigger when dm4 = 0 interrupt number 4 (int3) priority level 000: interrupt disabled 001-111: 1-7 when dm4 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-50 31 30 29 28 27 26 25 24 imc2 bit symbol eimb1 eimb0 dmb ilb2 ilb1 ilb0 (0xffff_e008) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 11 as dma trigger when dmb = 0 interrupt number 11 (int6) priority level 000: interrupt disabled 001-111: 1-7 when dmb = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eima1 eima0 dma ila2 ila1 ila0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 10 as dma trigger when dma = 0 interrupt number 10 (int5) priority level 000: interrupt disabled 001-111: 1-7 when dma = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim91 eim90 dm9 il92 il91 il90 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 9 as dma trigger when dm9 = 0 interrupt number 9 (inttx6) priority level 000: interrupt disabled 001-111: 1-7 when dm9 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim81 eim80 dm8 il82 il81 il80 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 8 as dma trigger when dm8 = 0 interrupt number 8 (intrx6) priority level 000: interrupt disabled 001-111: 1-7 when dm8 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-51 31 30 29 28 27 26 25 24 imc3 bit symbol eimf1 eimf0 dmf ilf2 ilf1 ilf0 (0xffff_e00c) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 15 as dma trigger when dmf = 0 interrupt number 15 (inta) priority level 000: interrupt disabled 001-111: 1-7 when dmf = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eime1 eime0 dme ile2 ile1 ile0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 14 as dma trigger when dme = 0 interrupt number 15 (int9) priority level 000: interrupt disabled 001-111: 1-7 when dme = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eimd1 eimd0 dmd ild2 ild1 ild0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 13 as dma trigger when dmd = 0 interrupt number 13 (int8) priority level 000: interrupt disabled 001-111: 1-7 when dmd = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eimc1 eimc0 dmc ilc2 ilc1 ilc0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable interrupt number 12 as dma trigger when dmc = 0 interrupt number 12 (int7) priority level 000: interrupt disabled 001-111: 1-7 when dmc = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-52 31 30 29 28 27 26 25 24 imc4 bit symbol eim131 eim130 dm13 il132 il131 il130 (0xffff_e010) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 19 as dma trigger when dm13 = 0 interrupt number 19 (inttx1) priority level 000: interrupt disabled 001-111: 1-7 when dm13 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim121 eim120 dm12 il122 il121 il120 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 18 as dma trigger when dm12 = 0 interrupt number 18 (intrx1) priority level 000: interrupt disabled 001-111: 1-7 when dm12 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim111 eim110 dm11 il112 il111 il110 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 17 as dma trigger when dm11 = 0 interrupt number 17 (inttx0) priority level 000: interrupt disabled 001-111: 1-7 when dm11 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim101 eim100 dm10 il102 il101 il100 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 16 as dma trigger when dm10 = 0 interrupt number 16 (intrx0) priority level 000: interrupt disabled 001-111: 1-7 when dm10 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-53 31 30 29 28 27 26 25 24 imc5 bit symbol eim171 eim170 dm17 il172 il171 il170 (0xffff_e014) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 23 as dma trigger when dm17 = 0 interrupt number 23 (intadhp) priority level 000: interrupt disabled 001-111: 1-7 when dm17 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim161 eim160 dm16 il162 il161 il160 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 22 as dma trigger when dm16 = 0 interrupt number 22 (inttx2) priority level 000: interrupt disabled 001-111: 1-7 when dm16 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim151 eim150 dm15 il152 il151 il150 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 21 as dma trigger when dm15 = 0 interrupt number 21 (intrx2) priority level 000: interrupt disabled 001-111: 1-7 when dm15 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim141 eim140 dm14 il142 il141 il140 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 20 as dma trigger when dm14 = 0 interrupt number 20 (ints0) priority level 000: interrupt disabled 001-111: 1-7 when dm14 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-54 31 30 29 28 27 26 25 24 imc6 bit symbol eim1b1 eim1b0 dm1b il1b2 il1b1 il1b0 (0xffff_e018) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 27 as dma trigger when dm1b = 0 interrupt number 27 (inttag2) priority level 000: interrupt disabled 001-111: 1-7 when dm1b = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim1a1 eim1a0 dm1a il1a2 il1a1 il1a0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 26 as dma trigger when dm1a = 0 interrupt number 26 (inttag1) priority level 000: interrupt disabled 001-111: 1-7 when dm1a = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim191 eim190 dm19 il192 il191 il190 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 25 as dma trigger when dm19 = 0 interrupt number 25 (inttag0) priority level 000: interrupt disabled 001-111: 1-7 when dm19 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim181 eim180 dm18 il182 il181 il180 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 24 as dma trigger when dm18 = 0 interrupt number 24 (intadm) priority level 000: interrupt disabled 001-111: 1-7 when dm18 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-55 31 30 29 28 27 26 25 24 imc7 bit symbol eim1f1 eim1f0 dm1f il1f2 il1f1 il1f0 (0xffff_e01c) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 31 as dma trigger when dm1f = 0 interrupt number 31 (intrx3) priority level 000: interrupt disabled 001-111: 1-7 when dm1f = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim1e1 eim1e0 dm1e il1e2 il1e1 il1e0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 30 as dma trigger when dm1e = 0 interrupt number 30 (inttb1) priority level 000: interrupt disabled 001-111: 1-7 when dm1e = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim1d1 eim1d0 dm1d il1d2 il1d1 il1d0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 29 as dma trigger when dm1d = 0 interrupt number 29 (inttb0) priority level 000: interrupt disabled 001-111: 1-7 when dm1d = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim1c1 eim1c0 dm1c il1c2 il1c1 il1c0 read/write r/w reset value 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. TMP1962C10BXBG 2006-02-21 tmp1962-56 31 30 29 28 27 26 25 24 imc8 bit symbol eim231 eim230 dm23 il232 il231 il230 (0xffff_e020) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 35 as dma trigger when dm23 = 0 interrupt number 35 (intrx5) priority level 000: interrupt disabled 001-111: 1-7 when dm23 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim221 eim220 dm22 il222 il221 il220 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 34 as dma trigger when dm22 = 0 interrupt number 34 (inttx4) priority level 000: interrupt disabled 001-111: 1-7 when dm22 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim211 eim210 dm21 il212 il211 il210 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 33 as dma trigger when dm21 = 0 interrupt number 33 (intrx4) priority level 000: interrupt disabled 001-111: 1-7 when dm21 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim201 eim200 dm20 il202 il201 il200 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 32 as dma trigger when dm20 = 0 interrupt number 32 (inttx3) priority level 000: interrupt disabled 001-111: 1-7 when dm20 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-57 31 30 29 28 27 26 25 24 imc9 bit symbol eim271 eim270 dm27 il272 il271 il270 (0xffff_e024) read/write r/w reset value 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 23 22 21 20 19 18 17 16 bit symbol eim261 eim260 dm26 il262 il261 il260 read/write r/w reset value 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 15 14 13 12 11 10 9 8 bit symbol eim251 eim250 dm25 il252 il251 il250 read/write r/w reset value 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 7 6 5 4 3 2 1 0 bit symbol eim241 eim240 dm24 il242 il241 il240 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 36 as dma trigger when dm24 = 0 interrupt number 36 (inttx5) priority level 000: interrupt disabled 001-111: 1-7 when dm24 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-58 31 30 29 28 27 26 25 24 imca bit symbol eim2b1 eim2b0 dm2b il2b2 il2b1 il2b0 (0xffff_e028) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 43 as dma trigger when dm2b = 0 interrupt number 43 (intcmp0) priority level 000: interrupt disabled 001-111: 1-7 when dm2b = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim2a1 eim2a0 dm2a il2a2 il2a1 il2a0 read/write r/w reset value 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 15 14 13 12 11 10 9 8 bit symbol eim291 eim290 dm29 il292 il291 il290 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 41 as dma trigger when dm29 = 0 interrupt number 41 (intcapg1) priority level 000: interrupt disabled 001-111: 1-7 when dm29 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim281 eim280 dm28 il282 il281 il280 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 40 as dma trigger when dm28 = 0 interrupt number 40 (intcapg0) priority level 000: interrupt disabled 001-111: 1-7 when dm28 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-59 31 30 29 28 27 26 25 24 imcb bit symbol eim2f1 eim2f0 dm2f il2f2 il2f1 il2f0 (0xffff_e02c) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 47 as dma trigger when dm2f = 0 interrupt number 47 (intcmp4) priority level 000: interrupt disabled 001-111: 1-7 when dm2f = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim2e1 eim2e0 dm2e il2e2 il2e1 il2e0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 46 as dma trigger when dm2e = 0 interrupt number 46 (intcmp3) priority level 000: interrupt disabled 001-111: 1-7 when dm2e = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim2d1 eim2d0 dm2d il2d2 il2d1 il2d0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 45 as dma trigger when dm2d = 0 interrupt number 45 (intcmp2) priority level 000: interrupt disabled 001-111: 1-7 when dm2d = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim2c1 eim2c0 dm2c il2c2 il2c1 il2c0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 44 as dma trigger when dm2c = 0 interrupt number 44 (intcmp1) priority level 000: interrupt disabled 001-111: 1-7 when dm2c = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-60 31 30 29 28 27 26 25 24 imcc bit symbol eim331 eim330 dm33 il332 il331 il330 (0xffff_e030) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 51 as dma trigger when dm33 = 0 interrupt number 51 (intcmp6) priority level 000: interrupt disabled 001-111: 1-7 when dm33 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim321 eim320 dm32 il322 il321 il320 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: high level 10: setting prohibited 11: rising edge must be set to 01 when used for stop wake-up signaling; otherwise, must be set to 11. dma trigger 0: disable 1: enable interrupt number 50 as dma trigger when dm32 = 0 interrupt number 50 (inttb3) priority level 000: interrupt disabled 001-111: 1-7 when dm32 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim311 eim310 dm31 il312 il311 il310 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: high level 10: setting prohibited 11: rising edge must be set to 01 when used for stop wake-up signaling; otherwise, must be set to 11. dma trigger 0: disable 1: enable interrupt number 49 as dma trigger when dm31 = 0 interrupt number 49 (inttb2) priority level 000: interrupt disabled 001-111: 1-7 when dm31 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim301 eim300 dm30 il302 il301 il300 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 48 as dma trigger when dm30 = 0 interrupt number 48 (intcmp5) priority level 000: interrupt disabled 001-111: 1-7 when dm30 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-61 31 30 29 28 27 26 25 24 imcd bit symbol eim371 eim370 dm37 il372 il371 il370 (0xffff_e034) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: falling edge 11: rising edge must be set to 10. dma trigger 0: disable 1: enable interrupt number 55 as dma trigger when dm37 = 0 interrupt number 55 (intdma1) priority level 000: interrupt disabled 001-111: 1-7 when dm37 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim361 eim360 dm36 il362 il361 il360 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: falling edge 11: rising edge must be set to 10. dma trigger 0: disable 1: enable interrupt number 54 as dma trigger when dm36 = 0 interrupt number 54 (intdma0) priority level 000: interrupt disabled 001-111: 1-7 when dm36 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim351 eim350 dm35 il352 il351 il350 read/write r/w reset value 0 0 0 0 0 0 function must be set to 00. must be set to 0. must be set to 000. 7 6 5 4 3 2 1 0 bit symbol eim341 eim340 dm34 il342 il341 il340 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 52 as dma trigger when dm34 = 0 interrupt number 52 (intcmp7) priority level 000: interrupt disabled 001-111: 1-7 when dm34 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-62 31 30 29 28 27 26 25 24 imce bit symbol eim3b1 eim3b0 dm3b il3b2 il3b1 il3b0 (0xffff_e038) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: setting prohibited 11: rising edge must be set to 11. dma trigger 0: disable 1: enable interrupt number 59 as dma trigger when dm3b = 0 interrupt number 59 (intad) priority level 000: interrupt disabled 001-111: 1-7 when dm3b = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim3a1 eim3a0 dm3a il3a2 il3a1 il3a0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: high level 10: setting prohibited 11: setting prohibited must be set to 01. dma trigger 0: disable 1: enable interrupt number 58 as dma trigger when dm3a = 0 interrupt number 58 (intrtc) priority level 000: interrupt disabled 001-111: 1-7 when dm3a = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim391 eim390 dm39 il392 il391 il390 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: falling edge 11: setting prohibited must be set to 10. dma trigger 0: disable 1: enable interrupt number 57 as dma trigger when dm39 = 0 interrupt number 57 (intdma3) priority level 000: interrupt disabled 001-111: 1-7 when dm39 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim381 eim380 dm38 il382 il381 il380 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: falling edge 11: setting prohibited must be set to 10. dma trigger 0: disable 1: enable interrupt number 56 as dma trigger when dm38 = 0 interrupt number 56 (intdma2) priority level 000: interrupt disabled 001-111: 1-7 when dm38 = 1 dmac channel select 000-011: 0-3 100-111: 4-7 TMP1962C10BXBG 2006-02-21 tmp1962-63 31 30 29 28 27 26 25 24 imcf bit symbol eim3f1 eim3f0 dm3f il3f2 il3f1 il3f0 (0xffff_e03c) read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: falling edge 11: setting prohibited must be set to 10. dma trigger 0: disable 1: enable interrupt number 63 as dma trigger when dm3f = 0 interrupt number 63 (intdma7) priority level 000: interrupt disabled 001-111: 1-7 when dm3f = 1 dmac channel select 000-011: 0-3 100-111: 4-7 23 22 21 20 19 18 17 16 bit symbol eim3e1 eim3e0 dm3e il3e2 il3e1 il3e0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: falling edge 11: setting prohibited must be set to 10. dma trigger 0: disable 1: enable interrupt number 62 as dma trigger when dm3e = 0 interrupt number 62 (intdma6) priority level 000: interrupt disabled 001-111: 1-7 when dm3e = 1 dmac channel select 000-011: 0-3 100-111: 4-7 15 14 13 12 11 10 9 8 bit symbol eim3d1 eim3d0 dm3d il3d2 il3d1 il3d0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: falling edge 11: setting prohibited must be set to 10. dma trigger 0: disable 1: enable interrupt number 61 as dma trigger when dm3d = 0 interrupt number 61 (intdma5) priority level 000: interrupt disabled 001-111: 1-7 when dm3d = 1 dmac channel select 000-011: 0-3 100-111: 4-7 7 6 5 4 3 2 1 0 bit symbol eim3c1 eim3c0 dm3c il3c2 il3c1 il3c0 read/write r/w reset value 0 0 0 0 0 0 function interrupt sensitivity 00: setting prohibited 01: setting prohibited 10: falling edge 11: setting prohibited must be set to 10. dma trigger 0: disable 1: enable interrupt number 60 as dma trigger when dm3c = 0 interrupt number 60 (intdma4) priority level 000: interrupt disabled 001-111: 1-7 when dm3c = 1 dmac channel select 000-011: 0-3 100-111: 4-7 note 1: interrupt sensitivity must be programmed when interrupts are enabled. note 2 when an interrupt is used to trigger a dmac channel, that dmac channel must be put in ready state after the programming of the intc. TMP1962C10BXBG 2006-02-21 tmp1962-64 6.4.3 interrupt request clear register loading the eiclr[5:0] field of this register with the ivr[9:4] value of the ivr causes the corresponding interr upt to be cleared. 31 30 29 28 27 26 25 24 intclr bit symbol (0xffff_e060) read/write reset value function 23 22 21 20 19 18 17 16 bit symbol read/write reset value function 15 14 13 12 11 10 9 8 bit symbol read/write reset value function 7 6 5 4 3 2 1 0 bit symbol eiclr5 eiclr4 eiclr3 eiclr2 eiclr1 eiclr0 read/write w reset value ? ? ? ? ? ? function ivrl[9:4] value for an interrupt to be cleared note 1: an interrupt request must not be cleared before the tx19 core processor reads the ivr value. note 2: follow the steps below to disable a particu lar interrupt with the interrupt controller (intc). 1. globally disable the acceptance of interrupts by the core processor by clearing the iec bit of the status register. 2. disable the desired interrupt with the intc by cl earing the ilx[2:0] field of the imcxx register. 3. execute the sync instruction. 4. enable the acceptance of interrupts by the core processor by setting the iec bit of the status register. example: mtc0 r0, r31 ; _di () ; sb r0, imc ** ; imc ** = 0 ; sync ; _sync () ; mtc0 $sp, r31 ; _ei () ; TMP1962C10BXBG 2006-02-21 tmp1962-65 6.4.4 intcg registers (stop wake-up signaling) stop wake-up signaling 31 30 29 28 27 26 25 24 imcga0 bit symbol emcg31 emcg30 int3en (0xffff_ee10) read/write r/w r/w reset value 1 0 0 function int3 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int3 for standby wake-up signaling 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcg21 emcg20 int2en read/write r/w r/w reset value 1 0 0 function int2 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int2 for standby wake-up signaling 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg11 emcg10 int1en read/write r/w r/w reset value 1 0 0 function int1 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int1 for standby wake-up signaling 0: disable 1: enable 7 6 5 4 3 2 1 0 bit symbol emcg01 emcg00 int0en read/write r/w r/w reset value 1 0 0 function int0 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int0 for standby wake-up signaling 0: disable 1: enable TMP1962C10BXBG 2006-02-21 tmp1962-66 31 30 29 28 27 26 25 24 imcgb0 bit symbol (0xffff_ee14) read/write r/w r/w reset value 1 1 0 function must be set to 0. 23 22 21 20 19 18 17 16 bit symbol read/write r/w r/w reset value 1 0 0 function must be set to 0. 15 14 13 12 11 10 9 8 bit symbol emcg51 emcg50 kwupen read/write r/w r/w reset value 0 1 0 function kwup standby wake-up interrupt sensitivity 00: setting prohibited 01: high level 10: setting prohibited 11: setting prohibited must be set to 01. kwup for standby wake-up signaling 0: disable 1: enable 7 6 5 4 3 2 1 0 bit symbol emcg41 emcg40 int4en read/write r/w r/w reset value 1 0 0 function int4 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int4 for standby wake-up signaling 0: disable 1: enable TMP1962C10BXBG 2006-02-21 tmp1962-67 31 30 29 28 27 26 25 24 imcgc0 bit symbol emcgb1 emcgb0 int6en (0xffff_ee18) read/write r/w r/w reset value 1 0 0 function int6 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int6 for standby wake-up signaling 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcga1 emcga0 int5en read/write r/w r/w reset value 1 0 0 function int5 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int5 for standby wake-up signaling 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol read/write r/w r/w reset value 1 1 0 function must be set to 0. 7 6 5 4 3 2 1 0 bit symbol read/write r/w r/w reset value 1 1 0 function must be set to 0. TMP1962C10BXBG 2006-02-21 tmp1962-68 31 30 29 28 27 26 25 24 imcgd0 bit symbol emcgf1 emcgf0 intaen (0xffff_ee1c) read/write r/w r/w reset value 1 0 0 function inta standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge inta for standby wake-up signaling 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcge1 emcge0 int9en read/write r/w r/w reset value 1 0 0 function int9 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int9 for standby wake-up signaling 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcgd1 emcgd0 int8en read/write r/w r/w reset value 1 0 0 function int8 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int8 for standby wake-up signaling 0: disable 1: enable 7 6 5 4 3 2 1 0 bit symbol emcgc1 emcgc0 int7en read/write r/w r/w reset value 1 0 0 function int7 standby wake-up interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int7 for standby wake-up signaling 0: disable 1: enable TMP1962C10BXBG 2006-02-21 tmp1962-69 note 1: interrupt sensitivity must be programmed wh en interrupts are enabled for stop wake-up signaling. note 2: follow the steps below to use an interrupt. 1. enable the corresponding pin as an interrupt source if it is also used as a general-purpose port pin or has other functions. 2. specify the interrupt sensitivity during initialization. 3. clear any corresponding interrupt request. 4. enable the interrupt source. note 3: the interrupt sensitivity and other settings must be programmed when the interrupt is disabled. note 4: the tmp1962 supports the use of 15 interrupt sources for stop wake-up signaling: int0-inta, intrtc, inttb2/inttb3 and kwup0-kwupd. for int0-inta, the cg block controls whether these interrupt sources are enabled as wake-up signal sources and defines the interrupt sensitivity. for kwup0-kwupd, the cg block controls whether these interrupt sources are enabled as wake-up signal sources while the kwupstx defines the interrupt sensitivity. for the above 15 interrupt sources, the interrupt sensitivity field in the intc has no effect, but it must be set to "high-level." example: enabling the int0 interrupt imcga0 TMP1962C10BXBG 2006-02-21 tmp1962-70 31 30 29 28 27 26 25 24 eicrcg bit symbol (0xffff_ee20) read/write r e s e t v a l u e function 23 22 21 20 b i t s y m b o l read/write r e s e t v a l u e function 15 14 13 12 b i t s y m b o l read/write r e s e t v a l u e function 7 6 5 4 3 2 1 0 bit symbol icrcg3 icrcg2 icrcg1 icrcg0 read/write w reset value ? ? ? ? function clear the corresponding interrupt request. 0000: int0 0101: kwup 1010: int5 0001: int1 0110: reserved 1011: int6 0010: int2 0111: reserved 1100: int7 0011: int3 1000: reserved 1101: int8 0100: int4 1001: reserved 1110: int9 1111: inta note 6: to clear interrupts used for stop wake-up signaling, program the following registers: 1. for kwup, program the kwupclr. 2. for int0-inta, inttb2, inttb3, and intrtc, program both the eicrcg register in the cg block, shown above, and the intclr register in the intc block. 3. for other interrupt sources, program the intcrl register in the intc block. TMP1962C10BXBG 2006-02-21 tmp1962-71 7. i/o ports 7.1 port 0 (p00 - p07) eight port 0 pins can be individually programmed to function as discrete general-purpose i/o pins, the d[0:7] bits of the data bus, or the ad[0:7] bits of the address/data bus. the p0cr register controls the direction of the port 0 pins. upon reset, the p0cr register bits are cleared, configuring all port 0 pins as inputs. during external memory accesses, port 0 pins are automa tically configured as d[0: 7] or ad[0:7 ], with the p0cr register bits all cleared. if the busmd pin (port j1) is driven low upon reset, separate bus mode is selected (d[0:7]). if the busmd pin is driven high upon reset, multiplexed bus mode is selected (ad[0:7]). figure 7.1 port 0 (p00 - p07) internal data bus direction control (bitwise) output latch p0 read port 0 p00 - p07 (d0 - d7) (ad0 - ad7) output buffer p0 write p0cr write reset stop drive note: the above diagram does not depict the address/data bus function. TMP1962C10BXBG 2006-02-21 tmp1962-72 port 0 register 7 6 5 4 3 2 1 0 p0 bit symbol p07 p06 p05 p04 p03 p02 p01 p00 (0xffff_f003) read/write r/w reset value input mode (the output latch is cleared to 0.) port 0 control register 7 6 5 4 3 2 1 0 p0cr bit symbol p07c p06c p05c p04c p03c p02c p01c p00c (0xffff_f001) read/write w reset value 0 0 0 0 0 0 0 0 function 0: in, 1: out (functions as d7-d0 or ad7-ad0 during external memory accesses, wi th all bits cleared.) figure 7.2 port 0 registers TMP1962C10BXBG 2006-02-21 tmp1962-73 7.2 port 1 (p10 - p17) eight port 1 pins can be individually programmed to function as discrete general-purpose i/o pins, the d[8:15] bits of the data bus, the ad[8:15] bits of the address/data bus, or the a[8:15] bits of the address bus. the p1cr and p1fc registers select the direction and function of the port 1 pins. upon reset, the output latch (p1) bits are cleared to all 0s, and th e p1cr and p1fc register bits are clear ed to all 0s, configuring all port 1 pins as input port pins. for external memory accesses, po rt 1 pins must be configured as the address bus or address/data bus through the programming of the p1cr and p1fc. if the busmd pin (port j1) is driven low upon reset, separate bus mode is selected (d[8:15]). if the busmd pin is driven high upon reset, multiplexe d bus mode is selected (ad[8:15] or a[8:15]). figure 7.3 port 1 (p10 - p17) note: the above diagram does not depict the address/data bus function. function control (bitwise) direction control (bitwise) output latch p1 read port 1 p10 - p17 (d8 - d15) ( ad8 - ad15/a8 - a15 ) output buffer p1fc write p1 write p1cr write reset internal data bus stop drive TMP1962C10BXBG 2006-02-21 tmp1962-74 port 1 register 7 6 5 4 3 2 1 0 p1 bit symbol p17 p16 p15 p14 p13 p12 p11 p10 (0xffff_f002) read/write r/w reset value input mode (the output latch is cleared to 0.) port 1 control register 7 6 5 4 3 2 1 0 p1cr bit symbol p17c p16c p15c p14c p13c p12c p11c p10c (0xffff_f007) read/write w reset value 0 0 0 0 0 0 0 0 function refer to p1fc. port 1 function register 7 6 5 4 3 2 1 0 p1fc bit symbol p17f p16f p15f p14f p13f p12f p11f p10f (0xffff_f006) read/write w reset value 0 0 0 0 0 0 0 0 function p1fc/p1cr = 00: input port, 01: output port, 10: d15-d8 or ad15-ad8, 11: a15-a8 port 1 function settings p1fc TMP1962C10BXBG 2006-02-21 tmp1962-75 7.3 port 2 (p20 - p27) eight port 2 pins can be individually programmed to function as discrete general-purpose i/o pins, the a[0:7] bits of the address bus, or the a[16:23] bits of the address bus. the p2cr and p2fc registers select the direction and function of the port 2 pins. upon reset, the output latch (p2) bits are cleared to all 0s, and the p2cr and p2fc register bits are cleared to all 0s, configuring all port 2 pins as input port pins. for external memory accesses, port 2 pins must be configured as the address bus through the programming of the p2cr and p2fc. if the busmd pin (port j1) is driven low upon reset, separate bus mode is selected (a[16:23]). if the busmd pin is driven high upon reset, multiplexe d bus mode is selected (a[0:7] or a[16:23]). figure 7.5 port 2 (p20 - p27) direction control (bitwise) p2 read port 2 p20 - p27 (a16 - a23) (a0-a7/a16 - a23) output buffer p2 write p2fc write p2cr write s y b a a0 - a7 a16 - a23 reset internal data bus selector selector s y b a output latch function control (bitwise) stop drive TMP1962C10BXBG 2006-02-21 tmp1962-76 port 2 register 7 6 5 4 3 2 1 0 p2 bit symbol p27 p26 p25 p24 p23 p22 p21 p20 (0xffff_f011) read/write r/w reset value input mode (the output latch is cleared to 0.) port 2 control register 7 6 5 4 3 2 1 0 p2cr bit symbol p27c p26c p25c p24c p23c p22c p21c p20c (0xffff_f017) read/write w reset value 0 0 0 0 0 0 0 0 function refer to p2fc. port 2 function register 7 6 5 4 3 2 1 0 p2fc bit symbol p27f p26f p25f p24f p23f p22f p21f p20f (0xffff_f016) read/write w reset value 0 0 0 0 0 0 0 0 function p2fc/p2cr = 00: input port, 01: output port, 10: a7-a0, 11: a23-a16 port 2 function settings p2cr p2fc TMP1962C10BXBG 2006-02-21 tmp1962-77 7.4 port 3 (p30 - p37) eight port 3 pins can be individually programmed to func tion as either discrete general-purpose i/o pins or cpu control/status pins. in either case, p30 and p31 are output-only pins. the p3cr and p3fc registers select the direction and function of the port 3 pins. upon reset, the p30 and p31 output latch bits are set to 1 and the p32-p36 output latch bits are set to 1 if the rstpup pin is high, or cleared to 0 if the rstpup pin is low. if the busmd pin (port j1) is driven low upon reset, separate bus mode is selected, causing the p37 output latch bit to be set to 1. if the busmd pin is driven high upon reset, multiplexed bus mode is selected, causing the p37 output latch bit to be cleared to 0. bits 2 to 6 of the p3cr are cleared to 0 upon reset (bits 0 and 1 ar e not used). bit 7 of the p3cr is cleared to 0 in separate bus mode, or set to 1 in multiplexed bus mode. a ll bits of the p3fc register are cleared upon reset, configuring p30 and p31 as output port pins (high), p32-p36 as input port pins with pull-up enabled (if the rstpup is high) or disabled (if the rstpup is low), and p37 as an input port pin (in separate bus mode) or output port pin (in multiplexed bus mode). when p30 is configured as rd (p3fc.p30f = 1), the read strobe sign al is activated when external address space is accessed. likewise, when p31 is configured as wr (p3fc.p31f = 1), the write strobe signal is activated when external address space is accessed. while busak is asserted, the internal pull-up resistors for p32 and p36 are enabled, if the p3fc.p3xf bit is set to 1. figure 7.7 port 3 (p30, p31) rd , wr p3 read output buffer function control (bitwise) ? p30 ( rd ) p31 ( wr ) p3 write p3fc write reset internal data bus selector s output latch b a s TMP1962C10BXBG 2006-02-21 tmp1962-78 figure 7.8 port 3 (p32, p35, p36) p3 read output buffer function control (bitwise) direction control (bitwise) p32 ( hwr ) p35 ( busak ) p36 ( w/r ) p-ch p3 write p3fc write p3cr write reset internal data bus selector s a b stop drive s r output latch rstpup hwr , busak , w/r reset programmable pull-up resistor TMP1962C10BXBG 2006-02-21 tmp1962-79 figure 7.9 port 3 (p33, p34) p3 read output buffer direction control (bitwise) p34 ( busrq ) p-ch p3 write p3cr write reset internal data bus stop drive s r output latch rstpup reset programmable pull-up resistor internal busrq function control (bitwise) p3cr write p3 read output buffer direction control (bitwise) p33 ( wait / rdy ) p-ch p3 write p3cr write reset stop drive s r output latch rstpup reset programmable pull-up resistor internal wait / rdy internal data bus TMP1962C10BXBG 2006-02-21 tmp1962-80 figure 7.10 port 3 (p37) p3 read output buffer function control (bitwise) direction control (bitwise) p37 (ale) p3 write p3fc write p3cr write reset internal data bus selector s a b stop drive s r output latch busmd ale reset TMP1962C10BXBG 2006-02-21 tmp1962-81 port 3 register 7 6 5 4 3 2 1 0 p3 bit symbol p37 p36 p35 p34 p33 p32 p31 p30 (0xffff_f01b) read/write r/w reset value input mode output mode rstpup = 1 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) rstpup = 0 depends on the bus mode. 0 0 0 0 0 1 1 port 3 control register 7 6 5 4 3 2 1 0 p3cr bit symbol p37c p36c p35c p34c p33c p32c ? ? (0xffff_f019) read/write w reset value 0 0 0 0 0 function depends on the bus mode. 0: input, 1: output port 3 function register 7 6 5 4 3 2 1 0 p3fc bit symbol p37f p36f p35f p34f p33f p32f p31f p30f (0xffff_f018) read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: ale 0: port 1: w/r 0: port 1: busak 0: port 1: busrq 0: port/ wait 1: port/ rdy 0: port 1: hwr 0: port 1: wr 0: port 1: rd busrq settings p30 ( rd ) function settings p3fc TMP1962C10BXBG 2006-02-21 tmp1962-82 7.5 port 4 (p40 - p44) p40-p43 can be individually programmed to function as either discrete general-purpose i/o pins or programmable chip select ( 0cs - 3cs ) pins. p44 can be programmed to function as either a general-purpose i/o pin or a system clock output (scout) pin. the p4cr and p4fc registers select the direction and function of the port 4 pins. upon reset, the p40-p43 output latch bits are set to 1 if the rstpup pin is high, or cleared to 0 if the rstpup pin is low. the p44 output latch bit is set to 1 regardless of the state of the rstpup pin. the p4cr and p4fc register bits are cleared upon reset, configuring p40-p43 as input port pins with pull-up enabled (if the rstpup is high) or disabled (if the rstpup is low) , and p44 as an input port pin with pull-up disabled (regardless of the state of the rstpup pin). figure 7.12 port 4 (p40 - p43) p4 read output buffer function control (bitwise) direction control (bitwise) p40 ( 0cs ) p41 ( 1cs ) p42 ( 2cs ) p43 ( 3cs ) p-ch p4 write p4fc write p4cr write reset internal data bus selector s a b stop drive s r output latch rstpup 0cs , 1cs , 2cs , 3cs reset programmable pull-up resistor TMP1962C10BXBG 2006-02-21 tmp1962-83 figure 7.13 port 4 (p44) selector r function control (bitwise) r direction control (bitwise) internal data bus reset p4cr write p4 read f sys clock p44 (scout) y s b a p4fc write syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-84 port 4 register 7 6 5 4 3 2 1 0 p4 bit symbol ? ? ? p44 p43 p42 p41 p40 (0xffff_f01d) read/write r/w reset value input mode rstpup=1 1 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) rstpup=0 1 0 0 0 0 port 4 control register 7 6 5 4 3 2 1 0 p4cr bit symbol ? ? ? p44c p43c p42c p41c p40c (0xffff_f023) read/write w reset value 0 0 0 0 0 0: input, 1: output port 4 function register 7 6 5 4 3 2 1 0 p4fc bit symbol ? ? ? p44f p43f p42f p41f p40f (0xffff_f022) read/write w reset value 0 0 0 0 0 function 0: port 1: scout 0: port 1: cs 0 port (p40) 1 0cs 0 port (p41) 1 1cs 0 port (p42) 1 2cs 0 port (p43) 1 3cs figure 7.14 port 4 registers TMP1962C10BXBG 2006-02-21 tmp1962-85 7.6 port 5 (p50 - p57) eight port 5 pins can be individually programmed to function as discrete general-purpose i/o pins or the a[0:7] bits of the address bus. the p5cr and p5fc registers select the direction and function of the port 5 pins. upon reset, the output latch (p5) bits are set to all 1s, and the p5cr and p5fc register bits are cleared to all 0s, configuring all port 5 pins as input port pins. for external memory accesses, port 5 pins must be configured as the address bus through the programming of the p5cr and p5fc. note that port 5 pins can be used as address bus bits in separate bus mode only. if the busmd pin (port j1) is driven low upon reset, separate bus mode is selected. figure 7.15 port 5 (p50 - p57) direction control (bitwise) p5 read port 5 p50 - p57 (a0 - a7) output buffer p5 write p5fc write p5cr write a0 - a7 reset s y b a output latch function control (bitwise) selector internal data bus stop drive TMP1962C10BXBG 2006-02-21 tmp1962-86 port 5 register 7 6 5 4 3 2 1 0 p5 bit symbol p57 p56 p55 p54 p53 p52 p51 p50 (0xffff_f02b) read/write r/w reset value input mode (the output latch is set to 1.) port 5 control register 7 6 5 4 3 2 1 0 p5cr bit symbol p57c p56c p55c p54c p53c p52c p51c p50c (0xffff_f02f) read/write w reset value 0 0 0 0 0 0 0 0 function refer to p5fc. port 5 function register 7 6 5 4 3 2 1 0 p5fc bit symbol p57f p56f p55f p54f p53f p52f p51f p50f (0xffff_f02e) read/write w reset value 0 0 0 0 0 0 0 0 function p5fc/p5cr = 00: input port, 01: output port, 10: input port, 11: a7-a0 port 5 function settings p5cr p5fc TMP1962C10BXBG 2006-02-21 tmp1962-87 7.7 port 6 (p60 - p67) eight port 6 pins can be individually programmed to function as discrete general-purpose i/o pins or the a[8:15] bits of the address bus. the p6cr and p6fc regi sters select the direction and function of the port 6 pins. upon reset, the output latch (p6) bits are set to all 1s, and the p6cr and p6fc register bits are cleared to all 0s, configuring all port 6 pins as input port pins. for external memory accesses, port 6 pins must be configured as the address bus through the programming of the p6cr and p6fc. note that port 6 pins can be used as address bus bits in separate bus mode only. if the busmd pin (port j1) is driven low upon reset, separate bus mode is selected. figure 7.17 port 6 (p60 - p67) direction control (bitwise) p6 read port 6 p60 - p67 (a8 - a15) output buffer p6 write p6fc write p6cr write a8 - a15 reset internal data bus selector s y b a output latch function control (bitwise) stop drive TMP1962C10BXBG 2006-02-21 tmp1962-88 port 6 register 7 6 5 4 3 2 1 0 p6 bit symbol p67 p66 p65 p64 p63 p62 p61 p60 (0xffff_f02a) read/write r/w reset value input mode (the output latch is set to 1.) port 6 control register 7 6 5 4 3 2 1 0 p6cr bit symbol p67c p66c p65c p64c p63c p62c p61c p60c (0xffff_f02d) read/write w reset value 0 0 0 0 0 0 0 0 function refer to p6fc. port 6 function register 7 6 5 4 3 2 1 0 p6fc bit symbol p67f p66f p65f p64f p63f p62f p61f p60f (0xffff_f02c) read/write w reset value 0 0 0 0 0 0 0 0 function p6fc/p6cr = 00: input port, 01: output port, 10: input port, 11: a15-a8 port 6 function settings p6cr p6fc TMP1962C10BXBG 2006-02-21 tmp1962-89 7.8 port 7 (p70 - 77), port 8 (p80 - 87) and port 9 (p90 - 97) port 7-9 pins are input-only pins shared with the analog input pins of the a/d converter (adc). figure 7.19 port 7-9 (p70 - 77, p80 - 87, p90 - 97) ad read port 7 - 9 read port 7 - 9 p70 - p97 (an0 - an23) internal data bus channel selector a/d converter a/d conversion result register reset TMP1962C10BXBG 2006-02-21 tmp1962-90 port 7 register 7 6 5 4 3 2 1 0 p7 bit symbol p77 p76 p75 p74 p73 p72 p71 p70 0xffff_f043 read/write r reset value input mode port 8 register 7 6 5 4 3 2 1 0 p8 bit symbol p87 p86 p85 p84 p83 p82 p81 p80 0xffff_f042 read/write r reset value input mode port 9 register 7 6 5 4 3 2 1 0 p9 bit symbol p97 p96 p95 p94 p93 p92 p91 p90 0xffff_f041 read/write r reset value input mode figure 7.20 port 7 - 9 registers TMP1962C10BXBG 2006-02-21 tmp1962-91 7.9 port a (pa0 - pa7) eight port a pins can be individually programmed to fu nction as discrete general-purpose or dedicated i/o pins. the pacr register selects the direction of the port a pins. upon reset, the pa cr register bits are cleared to all 0s, configuring all port a pins as input port pins. pa0 and pa2 can be programmed as inputs to 8-bit timers. pa1 and pa3-pa7 can be programmed as outputs from 8-bit timers. setting the pafc register bits configures the corresponding port a pins for timer fu nctions. a reset clears the pacr and pafc register bits, configuring all port a pins as input port pins. figure 7.21 port a (pa0, pa2) function control (bitwise) direction control (bitwise) s output latch stop drive pafc write pacr write reset internal data bus b selector a pa write pa read pa0 (ta0in) pa2 (ta2in) s ta0in ta2in TMP1962C10BXBG 2006-02-21 tmp1962-92 figure 7.22 port a (pa1, pa3, pa4, pa5, pa6, pa7) function control (bitwise) direction control (bitwise) s output latch stop drive pafc write ta1out, ta7out ta3out, ta9out ta5out, tabout pacr write reset internal data bus s a selector b pa write s b selector a timer flip-flop output pa read pa1 (ta1out) pa3 (ta3out) pa4 (ta5out) pa5 (ta7out) pa6 (ta9out) pa7 (tabout) TMP1962C10BXBG 2006-02-21 tmp1962-93 port a register 7 6 5 4 3 2 1 0 pa bit symbol pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 0xffff_f040 read/write r/w reset value input mode (the output latch is set to 1.) port a control register 7 6 5 4 3 2 1 0 pacr bit symbol pa7c pa6c pa5c pa4c pa3c pa2c pa1c pa0c 0xffff_f044 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port a function register 7 6 5 4 3 2 1 0 pafc bit symbol pa7f pa6f pa5f pa4f pa3f pa2f pa1f pa0f 0xffff_f048 read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: tabout 0: port 1: ta9out 0: port 1: ta7out 0: port 1: ta5out 0: port 1: ta3out 0: port 1: ta2in 0: port 1: ta1out 0: port 1: ta0in figure 7.23 port a registers TMP1962C10BXBG 2006-02-21 tmp1962-94 7.10 port b (pb0 - pb7) eight port b pins can be individually programmed to fu nction as discrete general-purpose or dedicated i/o pins. the pbcr register selects the direction of the port b pins. upon reset, the pbcr register bits are cleared to all 0s, configuring all port b pins as input port pins. pb0, pb1, pb4 and pb7 can be programmed as outputs from 16-bit timers. pb2, pb3, pb5 and pb6 can be programmed as inputs to 16-bit timers or external interrupt request pins. setting the pbfc register bits configures the corresponding port b pins for dedicated functions. a reset clears the pbcr and pbfc register bits, configuring all port b pins as input port pins. figure 7.24 port b (pb0, pb1, pb4, pb7) function control (bitwise) direction control (bitwise) s output latch stop drive pbfc write tb0out tb1out tb2out tb3out pbcr write reset internal data bus s a selector b pb write s b selector a timer flip-flop output pb read pb0 (tb0out) pb1 (tb1out) pb4 (tb2out) pb7 (tb3out) TMP1962C10BXBG 2006-02-21 tmp1962-95 figure 7.25 port b (pb2, pb3, pb5, pb6) function control (bitwise) direction control (bitwise) s output latch stop drive pbfc write pbcr write reset internal data bus b selector a pb write pb read pb2 (tb2in0/int5) pb3 (tb2in1/int6) pb5 (tb3in0/int7) pb6 (tb3in1/int8) s tb2in0, tb2in1 tb3in0, tb3in1 int5, 6, 7, 8 TMP1962C10BXBG 2006-02-21 tmp1962-96 port b register 7 6 5 4 3 2 1 0 pb bit symbol pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 0xffff_f053 read/write r/w reset value input mode (the output latch is set to 1.) port b control register 7 6 5 4 3 2 1 0 pbcr bit symbol pb7c pb6c pb5c pb4c pb3c pb2c pb1c pb0c 0xffff_f057 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port b function register 7 6 5 4 3 2 1 0 pbfc bit symbol pb7f pb6f pb5f pb4f pb3f pb2f pb1f pb0f 0xffff_f05b read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: tb3out 0: port 1: tb3in1 int8 0: port 1: tb3in0 int7 0: port 1: tb2out 0: port 1: tb2in1 int6 0: port 1: tb2in0 int5 0: port 1: tb1out 0: port 1: tb0out function corresponding bit in pbfc corresponding bit in pbcr port used tb0out output settings 1 1 pb0 tb1out output settings 1 1 pb1 tb2in0 input settings 1 0 int5 input settings 1 ( * 1) 0 pb2 tb2in1 input settings 1 0 int6 input settings 1 ( * 1) 0 pb3 tb2out output settings 1 1 pb4 tb3in0 input settings 1 0 int7 input settings 1( * 1) 0 pb5 tb3in1 input settings 1 0 int8 input settings 1( * 1) 0 pb6 tb3out output settings 1 1 pb7 * 1: this bit must be set when the corresponding interrupt source is used for stop wake-up signaling with syscr.drve cleared to 0. otherwise, the bit need not be set. figure 7.26 port b registers note: for a port pin assigned two input functions in addition to the port function, the corresponding function modules must be programmed to determine which function is enabled. TMP1962C10BXBG 2006-02-21 tmp1962-97 7.11 port c (pc0 - pc7) eight port c pins can be individually programmed to fu nction as discrete general-purpose or dedicated i/o pins. the pccr register selects the direction of the port c pins. upon reset, the pccr register bits are cleared to all 0s, configuring all port c pins as input port pins. pc0, pc3 and pc6 can be programmed as sio data outputs. pc1, pc4 and pc7 can be programmed as sio data inputs. pc2 and pc5 can be programmed as sio clock inputs/outputs or cts inputs. setting the pcfc regist er bits configures the corr esponding port c pins for dedicated functions. a reset clears the pccr and pcfc regist er bits, configuring all port c pins as input port pins. figure 7.27 port c (pc0, pc3, pc6) function control (bitwise) direction control (bitwise) s output latch stop drive pcfc write txd0 output txd1 output txd2 output pccr write reset internal data bus pc write pc read pc0 (txd0) pc3 (txd1) pc6 (txd2) configurable as open-drain outputs pcode TMP1962C10BXBG 2006-02-21 tmp1962-98 figure 7.28 port c (pc1, pc4, pc7) function control (bitwise) direction control (bitwise) s output latch stop drive pcfc write pccr write reset internal data bus b selector a pc write pc read pc1 (rxd0) pc4 (rxd1) pc7 ( rxd2 ) s rxd0 input rxd1 input rxd2 in p ut TMP1962C10BXBG 2006-02-21 tmp1962-99 figure 7.29 port c (pc2, pc5) function control (bitwise) direction control (bitwise) s output latch stop drive pcfc write sclk0 output sclk1 output pccr write reset internal data bus pc write pc read pc2 (sclk0/ 0cts ) pc5 (sclk1/ 1cts ) 0cts , 1cts sclk0, sclk1 configurable as open-drain outputs pcode TMP1962C10BXBG 2006-02-21 tmp1962-100 port c register 7 6 5 4 3 2 1 0 pc bit symbol pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0xffff_f052 read/write r/w reset value input mode (the output latch is set to 1.) port c control register 7 6 5 4 3 2 1 0 pccr bit symbol pc7c pc6c pc5c pc4c pc3c pc2c pc1c pc0c 0xffff_f056 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port c function register 7 6 5 4 3 2 1 0 pcfc bit symbol pc7f pc6f pc5f pc4f pc3f pc2f pc1f pc0f 0xffff_f05a read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: rxd2 0: port 1: txd2 0: port 1: sclk1 1cts 0: port 1: rxd1 0: port 1: txd1 0: port 1: sclk0 0cts 0: port 1: rxd0 0: port 1: txd0 port c open-drain enable register 7 6 5 4 3 2 1 0 pcode bit symbol - pcode6 pcode5 - pcode3 pcode2 - pcode0 0xffff_f05e read/write w w w reset value 0 0 0 0 0 function 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain figure 7.30 port c registers TMP1962C10BXBG 2006-02-21 tmp1962-101 7.12 port d (pd0 - pd7) eight port d pins can be individually programmed to function as discrete general-purpose or dedicated i/o pins. the pdcr register selects the direction of the port d pins. upon reset, the pdcr register bits are cleared to all 0s, configuring all port d pins as input port pins. pd0, pd3 and pd6 can be programmed as sio clock inputs/outputs or cts inputs. pd1 and pd4 can be programmed as sio data outputs. pd2 and pd5 can be programmed as sio data inputs. pd7 can be programm ed as a key-pressed wake-up input. setting the pdfc register bits configures the corresponding port d pi ns for dedicated functions. a reset clears the pdcr and pdfc register bits, configuring all port d pins as input port pins. pd7 has an internal pull-up resistor, which is enabled when key input is enabled through the programming of kwupstn with the kwupcnt.kype bit set to 1 in the key-pressed wake-up circuit block. for details, refer to chapter 19. the pull-up resistor is disabled when the pd7 pin is used as a general-purpose i/o pin. figure 7.31 port d (pd0, pd3, pd6) function control (bitwise) direction control (bitwise) s output latch stop drive pdfc write sclk2 output sclk3 output sclk4 output pdcr write reset internal data bus pd write pd read pd0 (sclk2/ 2cts ) pd3 (sclk3/ 3cts ) pd6 (sclk4/ 4cts ) 2cts , 3cts 4cts sclk2, sclk3 sclk4 configurable as open-drain outputs pdode TMP1962C10BXBG 2006-02-21 tmp1962-102 figure 7.32 port d (pd1, pd4) figure 7.33 port d (pd2, pd5) function control (bitwise) direction control (bitwise) s output latch stop drive pdfc write pdcr write reset internal data bus b selector a pd write pd read pd2 (rxd3) pd5 (rxd4) s rxd3 input rxd4 input function control (bitwise) direction control (bitwise) s output latch stop drive pdfc write txd3 output txd4 output pdcr write reset internal data bus pd write pd read pd1 (txd3) pd4 (txd4) a selector b s b selector a s configurable as open-drain outputs pdode TMP1962C10BXBG 2006-02-21 tmp1962-103 figure 7.34 port d (pd7) key8 function control (bitwise) direction control (bitwise) s output latch stop drive pdfc write pdcr write reset internal data bus b selector a pd write pd read pd7 (key8) s reset TMP1962C10BXBG 2006-02-21 tmp1962-104 port d register 7 6 5 4 3 2 1 0 pd bit symbol pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 0xffff_f051 read/write r/w reset value input mode (the output latch is set to 1.) port d control register 7 6 5 4 3 2 1 0 pdcr bit symbol pd7c pd6c pd5c pd4c pd3c pd2c pd1c pd0c 0xffff_f055 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port d function register 7 6 5 4 3 2 1 0 pdfc bit symbol pd7f pd6f pd5f pd4f pd3f pd2f pd1f pd0f 0xffff_f059 read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: key8 0: port 1: sclk4 4cts 0: port 1: rxd4 0: port 1: txd4 0: port 1: sclk3 3cts 0: port 1: rxd3 0: port 1: txd3 0: port 1: sclk2 2cts port d open-drain enable register 7 6 5 4 3 2 1 0 pdode bit symbol ? pdode6 ? pdode4 pdode3 ? pdode1 pdode0 0xffff_f05d read/write w w w reset value 0 0 0 0 0 function 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain figure 7.35 port d registers TMP1962C10BXBG 2006-02-21 tmp1962-105 7.13 port e (pe0 - pe7) eight port e pins can be individually programmed to f unction as discrete general-purpose or dedicated i/o pins. the pecr register selects the direction of the port e pins. upon reset, the pecr register bits are cleared to all 0s, configuring all port e pins as input port pins. pe0 can be programmed as an sio data output. pe1 can be programmed as an sio data input. pe2 can be programmed as an sio clock input/output or cts input. pe3-pe7 can be programmed as key-pressed wake-up in puts. setting the pefc register bits configures the corresponding port e pins for dedicated functions. a reset clears the pecr and pefc register bits, configuring all port e pins as input port pins. pe3-pe7 have internal pull-up resistors, which ar e enabled when key input is enabled through the programming of kwupstn with the kwupcnt.kype bit set to 1 in the key-pressed wake-up circuit block. for details, refer to chapter 19. the pull-up resistors are disabled when the pe3-pe7 pins are used as general-purpose i/o pins. figure 7.36 port e (pe0) function control (bitwise) direction control (bitwise) s output latch stop drive pefc write txd5 output pecr write reset internal data bus pe write pe read pe0 (txd5) configurable as an open-drain output peode TMP1962C10BXBG 2006-02-21 tmp1962-106 figure 7.37 port e (pe1) figure 7.38 port e (pe2) function control (bitwise) direction control (bitwise) s output latch stop drive pefc write pecr write reset internal data bus b selector a pe write pe read pe1 (rxd5) s rxd5 input function control (bitwise) direction control (bitwise) s output latch stop drive pefc write sclk5 output pecr write reset internal data bus pe write pe read pe2 (sclk5/ 5cts ) 5cts sclk5 configurable as an open-drain output peode TMP1962C10BXBG 2006-02-21 tmp1962-107 figure 7.39 port e (pe3, pe4, pe5, pe6, pe7) key9, keya keyb, keyc keyd function control (bitwise) direction control (bitwise) s output latch stop drive pefc write pecr write reset internal data bus b selector a pe write pe read pe3 (key9), pe4(keya) pe5 (keyb), pe6(keyc) pe7 (keyd) s reset TMP1962C10BXBG 2006-02-21 tmp1962-108 port e register 7 6 5 4 3 2 1 0 pe bit symbol pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 0xffff_f050 read/write r/w reset value input mode (the output latch is set to 1.) port e control register 7 6 5 4 3 2 1 0 pecr bit symbol pe7c pe6c pe5c pe4c pe3c pe2c pe1c pe0c 0xffff_f054 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port e function register 7 6 5 4 3 2 1 0 pefc bit symbol pe7f pe6f pe5f pe4f pe3f pe2f pe1f pe0f 0xffff_f058 read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: keyd 0: port 1: keyc 0: port 1: keyb 0: port 1: keya 0: port 1: key9 0: port 1: sclk5 5cts 0: port 1: rxd5 0: port 1: txd5 port e open-drain enable register 7 6 5 4 3 2 1 0 peode bit symbol ? ? ? ? ? peode2 ? peode0 0xffff_f05c read/write w w reset value 0 0 function 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain figure 7.40 port e registers TMP1962C10BXBG 2006-02-21 tmp1962-109 7.14 port f (pf0 - pf7) eight port f pins can be individually programmed to f unction as discrete general-purpose or dedicated i/o pins. the pfcr register selects the direction of the port f pins. upon reset, the pfcr register bits are cleared to all 0s, configuring all port f pins as input port pins. pf0-pf2 can be programmed as sbi inputs/outputs. pf3 and pf5 can be programmed as dma request signal inputs. pf4 and pf6 can be programmed as dma acknowledge signal outputs. pf7 can be programmed as a clock source input for the 32-bit time base timer. setting the pffc register bits configures the correspondi ng port f pins for dedicated functions. a reset clears the pfcr and pffc register bits, configurin g all port f pins as input port pins. figure 7.41 port f (pf0) function control (bitwise) direction control (bitwise) s output latch stop drive pffc write so output sda output pfcr write reset internal data bus pf write pf read pf0 (so/sda) configurable as an open-drain output pfode TMP1962C10BXBG 2006-02-21 tmp1962-110 figure 7.42 port f (pf1) function control (bitwise) direction control (bitwise) s output latch stop drive pffc write scl output pfcr write reset internal data bus pf write pf read pf1 (si/scl) configurable as an open-drain output pfode TMP1962C10BXBG 2006-02-21 tmp1962-111 figure 7.43 port f (pf2) function control (bitwise) direction control (bitwise) s output latch stop drive pffc write sck output pfcr write reset internal data bus pf write pf read pf2 (sck) a selector b s b selector a s reset sck input TMP1962C10BXBG 2006-02-21 tmp1962-112 figure 7.44 port f (pf3, pf5) figure 7.45 port f (pf4, pf6) function control (bitwise) direction control (bitwise) s output latch stop drive pffc write pfcr write reset internal data bus b selector a pf write pf read pf3 ( 2dreq ) pf5 ( 3dreq ) s 2dreq input 3dreq input function control (bitwise) direction control (bitwise) s output latch stop drive pofc write 2dack output 3dack output pocr write reset internal data bus s a selector b po write s b selector a po read pf4 ( 2dack ) pf6 ( 3dack ) TMP1962C10BXBG 2006-02-21 tmp1962-113 figure 7.46 port f (pf7) function control (bitwise) direction control (bitwise) s output latch stop drive pffc write pfcr write reset internal data bus b selector a pf write pf read pf7 (tbtin) s tbtin TMP1962C10BXBG 2006-02-21 tmp1962-114 port f register 7 6 5 4 3 2 1 0 pf bit symbol pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 0xffff_f063 read/write r/w reset value input mode (the output latch is set to 1.) port f control register 7 6 5 4 3 2 1 0 pfcr bit symbol pf7c pf6c pf5c pf4c pf3c pf2c pf1c pf0c 0xffff_f067 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port f function register 7 6 5 4 3 2 1 0 pffc bit symbol pf7f pf6f pf5f pf4f pf3f pf2f pf1f pf0f 0xffff_f06b read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: tbtin 0: port 1: 3dack 0: port 1: 3dreq 0: port 1: 2dack 0: port 1: 2dreq 0: port 1: sck 0: port 1: si scl 0: port 1: so sdao port f open-drain enable register 7 6 5 4 3 2 1 0 pfode bit symbol ? ? ? ? ? ? pfode1 pfode0 0xffff_f06f read/write w reset value 0 0 function 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain figure 7.47 port f registers TMP1962C10BXBG 2006-02-21 tmp1962-115 7.15 port g (pg0 - pg7) eight port g pins can be individually programmed to fu nction as discrete general-purpose i/o pins or 32-bit capture trigger input pins. the pgcr register selects th e direction of the port g pins. upon reset, the pgcr register bits are cleared to all 0s, configuring all port g pins as input port pins. setting the pgfc register bits configures the corres ponding port g pins as 32-bit capture trigger inputs. a reset clears the pgcr and pgfc register bits, configuring all port g pins as input port pins. figure 7.48 port g (pg0 - pg7) function control (bitwise) direction control (bitwise) s output latch stop drive pgfc write pgcr write reset internal data bus b selector a pg write pg read pg0 (tc0in) pg1 (tc1in) pg2 (tc2in) pg3 (tc3in) pg4 (tc4in) pg5 (tc5in) pg6 (tc6in) pg7 (tc7in) s tc0in, tc1in tc2in, tc3in tc4in, tc5in tc6in, tc7in TMP1962C10BXBG 2006-02-21 tmp1962-116 port g register 7 6 5 4 3 2 1 0 pg bit symbol pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 0xffff_f062 read/write r/w reset value input mode (the output latch is set to 1.) port g control register 7 6 5 4 3 2 1 0 pgcr bit symbol pg7c pg6c pg5c pg4c pg3c pg2c pg1c pg0c 0xffff_f066 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port g function register 7 6 5 4 3 2 1 0 pgfc bit symbol pg7f pg6f pg5f pg4f pg3f pg2f pg1f pg0f 0xffff_f06a read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: tc7in 0: port 1: tc6in 0: port 1: tc5in 0: port 1: tc4in 0: port 1: tc3in 0: port 1: tc2in 0: port 1: tc1in 0: port 1: tc0in figure 7.49 port g registers TMP1962C10BXBG 2006-02-21 tmp1962-117 7.16 port h (ph0 - ph7) eight port h pins can be individually programmed to fu nction as discrete general-purpose i/o pins or 32-bit compare output pins. the phcr register selects the direction of the port h pins. upon reset, the phcr register bits are cleared to all 0s, configuring all port h pins as input port pins. setting the phfc register bits configures the corresponding port h pins as 32-b it compare outputs. a reset clears the phcr and phfc register bits, configuring all port h pins as input port pins. figure 7.50 port h (ph0 - ph7) function control (bitwise) direction control (bitwise) s output latch stop drive phfc write tc0out, tc1out tc2out, tc3out tc4out, tc5out tc6out, tc7o ut phcr write reset internal data bus s a selector b ph write s b selector a timer flip-flop output ph read ph0 (tc0out) ph1 (tc1out) ph2 (tc2out) ph3 (tc3out) ph4 (tc4out) ph5 (tc5out) ph6 (tc6out) ph7 (tc7out) TMP1962C10BXBG 2006-02-21 tmp1962-118 port h register 7 6 5 4 3 2 1 0 ph bit symbol ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 0xffff_f061 read/write r/w reset value input mode (the output latch is set to 1.) port h control register 7 6 5 4 3 2 1 0 phcr bit symbol ph7c ph6c ph5c ph4c ph3c ph2c ph1c ph0c 0xffff_f065 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port h function register 7 6 5 4 3 2 1 0 phfc bit symbol ph7f ph6f ph5f ph4f ph3f ph2f ph1f ph0f 0xffff_f069 read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: tcout7 0: port 1: tcout6 0: port 1: tcout5 0: port 1: tcout4 0: port 1: tcout3 0: port 1: tcout2 0: port 1: tcout1 0: port 1: tcout0 figure 7.51 port h registers TMP1962C10BXBG 2006-02-21 tmp1962-119 7.17 port i (pi0 - pi7) eight port i pins can be individually programmed to function as discrete general-purpose i/o pins or dedicated input pins. the picr register selects the direction of the port i pins. upon reset, the picr register bits are cleared to all 0s, configuring all port i pins as input port pins. pi0 can be programmed as an trigger input for the a/d converter. pi1-pi6 can be programmed as external interrupt sources. setting the pifc register bits configures the corresponding port i pins for dedicated functions. a re set clears the picr and pifc register bits, configuring all port i pins as input port pins. figure 7.52 port i (pi0) function control (bitwise) direction control (bitwise) s output latch stop drive pifc write picr write reset internal data bus b selector a pi write pi read pi0 ( adtrg ) s adtrg TMP1962C10BXBG 2006-02-21 tmp1962-120 figure 7.53 port i (pi1 - pi6) figure 7.54 port i (pi7) function control (bitwise) direction control (bitwise) s output latch stop drive pi write picr write reset internal data bus pi1 (int1), pi2 (int2) pi3 (int3), pi4 (int4) pi5 (int9), pi6 (inta) output buffer reset pi read int1, int2, int3, int4, int9, inta pi read output buffer direction control (bitwise) pi7 pi write picr write reset stop drive internal data bus s output latch TMP1962C10BXBG 2006-02-21 tmp1962-121 port i register 7 6 5 4 3 2 1 0 pi bit symbol pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 0xffff_f060 read/write r/w reset value input mode (the output latch is set to 1.) port i control register 7 6 5 4 3 2 1 0 picr bit symbol pi7c pi6c pi5c pi4c pi3c pi2c pi1c pi0c 0xffff_f064 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port i function register 7 6 5 4 3 2 1 0 pifc bit symbol ? pi6f pi5f pi4f pi3f pi2f pi1f pi0f 0xffff_f068 read/write w reset value 0 0 0 0 0 0 0 function 0: port 1: inta 0: port 1: int9 0: port 1: int4 0: port 1: int3 0: port 1: int2 0: port 1: int1 0: port 1: * adtrg function corresponding bit in pifc corresponding bit in picr port used adtrg output settings 1 0 pi0 int1 input settings 1 ( * 1) 0 pi1 int2 input settings 1 ( * 1) 0 pi2 int3 input settings 1 ( * 1) 0 pi3 int4 input settings 1 ( * 1) 0 pi4 int9 input settings 1 ( * 1) 0 pi5 inta input settings 1 ( * 1) 0 pi6 figure 7.55 port i registers * 1: this bit must be set when the corresponding interrupt source is used for stop wake-up signaling with syscr.drve cleared to 0. otherwise, the bit need not be set. TMP1962C10BXBG 2006-02-21 tmp1962-122 7.18 port j (pj0 - pj4) five port j pins can be individually programmed to function as discrete general-purpose i/o pins or dedicated input pins. the pjcr register selects the direction of the port j pins. upon reset, the pjcr register bits are cleared to all 0s, configuring all port j pins as input port pins. pj0 can be programmed as an external interrupt source. setting the corresponding pjfc register b it configures pj0 as an exte rnal interrupt source pin. a reset clears the pjcr and pjfc register bits, configuring all port j pins as input port pins. figure 7.56 port j (pj0) function control (bitwise) direction control (bitwise) s output latch stop drive pj write pjcr write reset internal data bus pj0 (int0) output buffer reset pj read int0 TMP1962C10BXBG 2006-02-21 tmp1962-123 figure 7.57 port j (pj1 - pj4) pj read output buffer direction control (bitwise) pj1 - pj4 pj write pjcr write reset stop drive internal data bus s output latch TMP1962C10BXBG 2006-02-21 tmp1962-124 port j register 7 6 5 4 3 2 1 0 pj bit symbol ? ? ? pj4 pj3 pj2 pj1 pj0 0xffff_f0c3 read/write r/w reset value input mode (the output latch is set to 1.) port j control register 7 6 5 4 3 2 1 0 pjcr bit symbol ? ? ? pj4c pj3c pj2c pj1c pj0c 0xffff_f0c7 read/write w reset value 0 0 0 0 0 function 0: input, 1: output port j function register 7 6 5 4 3 2 1 0 pjfc bit symbol ? ? ? ? ? ? ? pj0f 0xffff_f0cb read/write w reset value 0 function 0: port 1: int0 function corresponding bit in pjfc corresponding bit in pjcr port used int0 input settings 1 ( * 1) 0 pj0 figure 7.58 port j registers * 1: this bit must be set when the corresponding interrupt source is used for stop wake-up signaling with syscr.drve cleared to 0. otherwise, the bit need not be set. TMP1962C10BXBG 2006-02-21 tmp1962-125 7.19 port k (pk0 - pk7) eight port k pins can be individually programmed to function as discrete general-purpose i/o pins or key-pressed wake-up input pins. the pkcr register selects the direction of the port k pins. upon reset, the pkcr register bits are cleared to all 0s, configuring all port k pins as input port pins. setting the pkfc register bits configures the corresponding port k pins as key-pressed wake-up inputs. a reset clears the pkcr and pkfc register bits, configuring all port k pins as input port pins. pk0-pk7 have internal pull-up resistors, which ar e enabled when key input is enabled through the programming of kwupstn with the kwupcnt.kype bit set to 1 in the key-pressed wake-up circuit block. for details, refer to chapter 19. the pull-up resistors are disabled when the pk0-pk7 pins are used as general-purpose i/o pins. figure 7.59 port k (pk0 - pk7) key0, key1 key2, key3 key4, key5 key6, key7 keymen kype function control (bitwise) direction control (bitwise) s output latch stop drive pkfc write pkcr write reset internal data bus b selector a pk write pk read pk0 (key0), pk1(key1) pk2 (key2), pk3(key3) pk4 (key4), pk5(key5) pk6 (key6), pk7(key7) s reset TMP1962C10BXBG 2006-02-21 tmp1962-126 port k register 7 6 5 4 3 2 1 0 pk bit symbol pk7 pk6 pk5 pk4 pk3 pk2 pk1 pk0 0xffff_f0c2 read/write r/w reset value input mode (the output latch is set to 1.) port k control register 7 6 5 4 3 2 1 0 pkcr bit symbol pk7c pk6c pk5c pk4c pk3c pk2c pk1c pk0c 0xffff_f0c6 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port k function register 7 6 5 4 3 2 1 0 pkfc bit symbol pk7f pk6f pk5f pk4f pk3f pk2f pk1f pk0f 0xffff_f0ca read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: key7 0: port 1: key6 0: port 1: key5 0: port 1: key4 0: port 1: key3 0: port 1: key2 0: port 1: key1 0: port 1: key0 figure 7.60 port k registers TMP1962C10BXBG 2006-02-21 tmp1962-127 7.20 port l (pl0 - pl7) eight port l pins can be individually programmed to fu nction as discrete general-purpose i/o pins or timer input pins. the plcr register selects the direction of the port l pins. upon reset, the plcr register bits are cleared to all 0s, configuring all port l pins as input port pins. pl0-pl3 can be programmed as inputs to 8-bit timers. pl4-pl7 can be programmed as inputs to 16-bit timers. setting the plfc register bits configures the corresponding port l pins for timer functions. a reset clears the plcr and plfc register bits, configuring all port l pins as input port pins. figure 7.61 port l (pl0 - pl7) function control (bitwise) direction control (bitwise) s output latch stop drive plfc write plcr write reset internal data bus b selector a pl write pl read pl0 (ta4in) pl1 (ta6in) pl2 (ta8in) pl3 (taain) pl4 (tb0in0) pl5 (tb0in1) pl6 (tb1in0) pl7 (tb1in1) s ta4in, ta6in ta8in, taain tb0in0, tb0in1 tb1in0, tb1in1 TMP1962C10BXBG 2006-02-21 tmp1962-128 port l register 7 6 5 4 3 2 1 0 pl bit symbol pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 0xffff_f0c1 read/write r/w reset value input mode (the output latch is set to 1.) port l control register 7 6 5 4 3 2 1 0 plcr bit symbol pl7c pl6c pl5c pl4c pl3c pl2c pl1c pl0c 0xffff_f0c5 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port l function register 7 6 5 4 3 2 1 0 plfc bit symbol pl7f pl6f pl5f pl4f pl3f pl2f pl1f pl0f 0xffff_f0c9 read/write w reset value 0 0 0 0 0 0 0 0 function 0: port 1: tb1in1 0: port 1: tb1in0 0: port 1: tb0in1 0: port 1: tb0in0 0: port 1: taain 0: port 1: ta8in 0: port 1: ta6in 0: port 1: ta4in figure 7.62 port l registers TMP1962C10BXBG 2006-02-21 tmp1962-129 7.21 port m (pm0 - pm7) eight port m pins can be individually programmed to function as discrete general-purpose i/o pins. the pmcr register selects the direction of the port m pins. upon reset, the pmcr register bits are cleared to all 0s, configuring all port m pins as input port pins. figure 7.63 port m (pm0 - pm7) pm read output buffer direction control (bitwise) pm0 - pm7 pm write pmcr write reset stop drive internal data bus s output latch TMP1962C10BXBG 2006-02-21 tmp1962-130 port m register 7 6 5 4 3 2 1 0 pm bit symbol pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 0xffff_f0c0 read/write r/w reset value input mode (the output latch is set to 1.) port m control register 7 6 5 4 3 2 1 0 pmcr bit symbol pm7c pm6c pm5c pm4c pm3c pm2c pm1c pm0c 0xffff_f0c4 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output figure 7.64 port m registers TMP1962C10BXBG 2006-02-21 tmp1962-131 7.22 port n (pn0 - pn7) eight port n pins can be individually programmed to function as discrete general-purpose or dedicated i/o pins. the pncr register selects the direction of the port n pins. upon reset, the pncr register bits are cleared to all 0s, configuring all port n pins as input port pins. pn0 can be programmed as an sio data output. pn1 can be programmed as an sio data input. pn2 can be programmed as an sio clock input/output or cts input. setting the pnfc register bits configures the corresponding port n pins for dedicated functions. a reset clears the pncr and pnfc register bits, configuring all port n pins as input port pins. figure 7.65 port n (pn0) function control (bitwise) direction control (bitwise) s output latch stop drive pnfc write txd6 output pncr write reset internal data bus pn write pn read pn0 (txd6) configurable as an open-drain output pnode TMP1962C10BXBG 2006-02-21 tmp1962-132 figure 7.66 port n (pn1) figure 7.67 port n (pn2) function control (bitwise) direction control (bitwise) s output latch stop drive pnfc write pncr write reset internal data bus b selector a pn write pn read pn1 (rxd6) s rxd6 input function control (bitwise) direction control (bitwise) s output latch stop drive pnfc write sclk6 output pncr write reset internal data bus pn write pn read pn2 (sclk6/ 6cts ) 6cts input sclk6 input configurable as an open-drain output pnode TMP1962C10BXBG 2006-02-21 tmp1962-133 figure 7.68 port n (pn3 - pn7) pn read output buffer direction control (bitwise) pn3 - pn7 pn write pncr write reset stop drive internal data bus s output latch TMP1962C10BXBG 2006-02-21 tmp1962-134 port n register 7 6 5 4 3 2 1 0 pn bit symbol pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 0xffff_f0d3 read/write r/w reset value input mode (the output latch is set to 1.) port n control register 7 6 5 4 3 2 1 0 pncr bit symbol pn7c pn6c pn5c pn4c pn3c pn2c pn1c pn0c 0xffff_f0d7 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output port n function register 7 6 5 4 3 2 1 0 pnfc bit symbol ? ? ? ? ? pn2f pn1f pn0f 0xffff_f0db read/write w reset value 0 0 0 function 0: port 1: sclk6 * cts6 0: port 1: rxd6 0: port 1: txd6 port n open-drain enable register 7 6 5 4 3 2 1 0 pnode bit symbol ? ? ? ? ? pnode2 ? pnode0 0xffff_f0df read/write w w reset value 0 0 function 0: cmos 1: open-dr ain 0: cmos 1: open-dr ain figure 7.69 port n registers TMP1962C10BXBG 2006-02-21 tmp1962-135 7.23 port o and port p (po0 - po7, pp0 - pp7) eight port o pins and eight port p pins can be individually programmed to function as discrete general-purpose i/o pins. the pocr and ppcr registers select the direction of the port o and p pins, respectively. upon reset, the pocr an d ppcr register bits are cleared to all 0s, configuring all port o and p pins as input port pins. figure 7.70 port o and port p (po0 - po7, pp0 - pp7) po/pp read output buffer direction control (bitwise) po0 - po7 pp0 - pp7 po/pp write pocr/ppcr write reset stop drive internal data bus s output latch TMP1962C10BXBG 2006-02-21 tmp1962-136 port o register 7 6 5 4 3 2 1 0 po bit symbol po7 po6 po5 po4 po3 po2 po1 po0 0xffff_f0d2 read/write r/w reset value input mode (the output latch is set to 1.) port o control register 7 6 5 4 3 2 1 0 pocr bit symbol po7c po6c po5c po4c po3c po2c po1c po0c 0xffff_f0d6 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output figure 7.71 port o registers port p register 7 6 5 4 3 2 1 0 pp bit symbol pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 0xffff_f0d1 read/write r/w reset value input mode (the output latch is set to 1.) port p control register 7 6 5 4 3 2 1 0 ppcr bit symbol pp7c pp6c pp5c pp4c pp3c pp2c pp1c pp0c 0xffff_f0d5 read/write w reset value 0 0 0 0 0 0 0 0 function 0: input, 1: output figure 7.72 port p registers TMP1962C10BXBG 2006-02-21 tmp1962-137 8. external bus interface the tmp1962 contains external bus inte rface logic that handles the transfer of information between the internal buses and the memory or peripherals in the external addres s space. it consists of the external bus interface (ebif) logic and the chip select/wait controller. the cs/wait controller provides four programmable chip select signals, with variable block sizes. the chip select function supports automatic wait-state generation an d data bus sizing (8-bit or 16-bit) for each of the four address blocks and the rest of the external address locations. the ebif logic controls the timing of the external bus, based on the settings of the cs/wait controller. the ebif logic also performs dynamic bus sizing and bus arbitration. ? external bus mode address/data separate bus mode or multiplexed bus mode ? wait-state generation individually programmable for each address block ? automatic insertion of up to seven wait cycles ? insertion of wait cycles through the wait / rdy pin ? data bus width individually programmable (8-bit or 16-bit) for each address block ? recovery cycles (read and write) individually programmable (to up to 2 cycles) fo r each address block. recovery cycles are dummy cycles inserted between two consecutive external bus cycles. ? bus arbitration TMP1962C10BXBG 2006-02-21 tmp1962-138 8.1 address and data buses (1) supported configurations the tmp1962 supports the selection of either separate bus mode or multiplexed bus mode. if the busmd pin (port j1) is driven low upon reset, sepa rate bus mode is selected. if the busmd pin is driven high upon reset, multiplexed bus mode is selected. for external memory interface, port 0, port 1, port 2, port 5 and port 6 pins can be configured as the address bus, data bus or address/data bus. table 8.1 shows the usage of the port pins in separate and multiplexed bus modes. table 8.1 usage of port pins in separate and multiplexed bus modes separate bus mode (busmd = l) multiplexed bus mode (busmd = h) port 0 (p00 - p07) d0 - d7 ad0 - ad7 port 1 (p10 - p17) d8 - d15 ad8 - ad15/a8 - a15 port 2 (p20 - p27) a16 - a23 a0 - a7/a16 - a23 port 5 (p50 - p57) a0 - a7 general-purpose port port 6 (p60 - p67) a8 - a15 general-purpose port port 3 (p37 only) general-purpose port ale upon reset, all port pins are configured as general- purpose input port pins. for external memory accesses, port pins must be configured as the address or data bus through the programming of the corresponding port control register (pncr) and port function register (pnfc). in multiplexed bus mode, the tmp1962 supports the fo llowing four bus configurations, according to the settings in the pncr and pnfc. table 8.2 address and data pins in multiplexed bus mode (1) (2) (3) (4) address lines max.24 ( - 16 mb) max.24 ( - 16 mb) max.16 ( - 64 kb) max.8 ( - 256 b) data lines 8 16 8 16 multiplexed address/data lines 8 16 0 0 port 0 ad0 - ad7 ad0 - ad7 ad0 - ad7 ad0 - ad7 port 1 a8 - a15 ad8 - ad15 a8 - a15 ad8 - ad15 pin functions port 2 a16 - a23 a16 - a23 a0 - a7 a0 - a7 timing diagram note 1: because the data bus is multiplexed with the address bus, even in the (3) and (4) configurations, address bits also appear on the ad bus prior to the data being accepted or provided. note 2: upon reset, all of ports 0-2 are configured as genera l-purpose input ports; programming is required to use them as address or data bus pins. note 3: address and data bus configurations are selectable through the programming of the p1cr, p1fc, p2cr and p2fc registers. (note 1) a7 - 0 a23 - 8 a23 - 8 a7 - 0 d7 - 0 ad7 - 0 ale a15 - 0 a23 - 16 a23 - 16 d15 - 0 ad15 - 0 ale a7 - 0 a15 - 0 a15 - 0 d7 - 0 ad7 - 0 ale a15 - 0 a7 - 0 d15 - 0 ad15 - 0 ale (note 1) rd rd rd rd TMP1962C10BXBG 2006-02-21 tmp1962-139 (2) states of the address bus during on-chip address accesses while an on-chip address is being accessed, the addr ess bus maintains the prev ious address externally presented. during this time, the data bus assumes the high -impedance state. 8.2 data formats this section shows the relationship between the external bus interface and the tmp1962 internal register assignments. (1) big-endian mode 1) word access ? 16-bit bus internal register external bus address d31 aa x0 bb x1 cc x2 d00 dd x3 ? 8-bit bus internal register external bus address d31 aa x0 bb x1 cc x2 d00 dd x3 2) halfword access ? 16-bit bus internal register external bus address d31 aa x0 d00 bb x1 address d31 cc x2 d00 dd x3 aabb ccdd msb lsb a1 = 0 a1 = 1 aa bb cc dd x0 x1 x2 x3 aabb msb lsb msb lsb ccdd msb lsb TMP1962C10BXBG 2006-02-21 tmp1962-140 ? 8-bit bus internal register external bus address d31 aa x0 d00 bb x1 internal register external bus address d31 cc x2 d00 dd x3 3) byte access ? 16-bit bus internal register external bus address d31 d00 aa x0 address d31 d00 bb x1 address d31 d00 cc x2 address d31 d00 dd x3 aa bb x0 x1 cc dd x2 x3 aa msb lsb bb msb lsb cc msb lsb dd msb lsb TMP1962C10BXBG 2006-02-21 tmp1962-141 ? 8-bit bus internal register external bus address d31 d00 aa x0 address d31 d00 bb x1 address d31 d00 cc x2 address d31 d00 dd x3 (2) little-endian mode 1) word access ? 16-bit bus internal register external bus address d31 dd x3 cc x2 bb x1 d00 aa x0 ? 8-bit bus internal register external bus address d31 dd x3 cc x2 bb x1 d00 aa x0 aa bb cc dd aabb ccdd lsb msb a1 = 0 a1 = 1 aa bb cc dd x0 x1 x2 x3 TMP1962C10BXBG 2006-02-21 tmp1962-142 2) halfword access ? 16-bit bus internal register external bus address d31 bb x1 d00 aa x0 address d31 dd x3 d00 cc x2 ? 8-bit bus internal register external bus address d31 bb x1 d00 aa x0 internal register external bus address d31 dd x3 d00 cc x2 aabb lsb msb ccdd lsb msb aa bb x0 x1 cc dd x2 x3 TMP1962C10BXBG 2006-02-21 tmp1962-143 3) byte access ? 16-bit bus internal register external bus address d31 d00 aa x0 address d31 d00 bb x1 address d31 d00 cc x2 address d31 d00 dd x3 ? 8-bit bus internal register external bus address d31 d00 aa x0 address d31 d00 bb x1 address d31 d00 cc x2 address d31 d00 dd x3 aa lsb msb bb lsb msb cc lsb msb dd lsb msb aa bb cc dd TMP1962C10BXBG 2006-02-21 tmp1962-144 8.3 external bus operation (separate bus mode) this section describes external bus operations. in the timing diagrams which follow, a23-a0 are used as the address bus, and d15-d0 are used as the data bus. (1) basic bus operation while the tmp1962 provides a total of three clock cycles to perform a read or write, it also allows the bus cycle to be extended by inserting wait states. the intern al system clock is also used as the basic clock for external bys cycles. figure 8.1 shows external bus read timing. figure 8.2 shows external bus write timing. while an on-chip address is being accessed, the external address bus maintains th e previous value. duri ng this time, the data bus assumes the high-impedance state, and bus control signals such as rd and wr remain inactive. figure 8.1 read cycle timing figure 8.2 write cycle timing data no change external access internal access d [15:0] hi-z tsys rd inactive a [23:0] csn external access internal access data no change inactive d [15:0] hi-z tsys a [23:0] csn wr TMP1962C10BXBG 2006-02-21 tmp1962-145 (2) wait timing the cs/wait controller provides three ways to insert wait states in a bus cycle for each address block: 1) inserting required number of wait state cy cles automatically (up to seven cycles) 2) using the wait pin to insert wait states dynamically (1+n, 3+n, 5+n or 7+n, where n is the number of wait stat e cycles inserted) 3) using the rdy pin to insert wait states dynamically (1+n, 3+n, 5+n or 7+n, where n is the number of wait state cycles inserted) the bnw bit of the cs/wait control register (bmncs ) defines the number of wait state cycles to be inserted automatically as well as external wait state input settings. figure 8.3 through 8.12 show bus cycle timings with wait states. figure 8.3 read cycle timing (with zero and automatically inserted one wait state) figure 8.4 read cycle timing (with automatically inserted five wait states) 0 wait state 1 wait state address address data data tsys a [23:0] d [15:0] rd 5 wait states tsys address data a [23:0] d [15:0] rd TMP1962C10BXBG 2006-02-21 tmp1962-146 figure 8.5 read cycle timing (with externally inserted (1 + n) wait states; n = 1) figure 8.6 read cycle timing (with externally inserted (3 + n) wait states; n = 1) figure 8.7 read cycle timing (with externally inserted (3 + n) wait states; n = 3) external (3 + n) wait states; n = 1 tsys address data a [23:0] d [15:0] rd wait address data external (3 + n) wait states; n = 3 tsys a [23:0] d [15:0] rd wait 0 wait state external (1 + n) wait states; n = 1 address address data data a [23:0] d [15:0] rd wait tsys TMP1962C10BXBG 2006-02-21 tmp1962-147 figure 8.8 write cycle timing (with zero and automatically inserted one wait state) figure 8.9 write cycle timing (with auto matically inserted five wait states) address address data data 0 wait state 1 wait state tsys a [23:0] d [15:0] wr tsys address data 5 wait states a [23:0] d [15:0] wr TMP1962C10BXBG 2006-02-21 tmp1962-148 figure 8.10 write cycle timing (with externally inserted (1 + n) wait states; n = 1) figure 8.11 write cycle timing (with externa lly inserted (3 + n) wait states; n = 1) figure 8.12 write cycle timing (with externally inserted (3 + n) wait states; n = 3) tsys address address data data 0 wait state external (1 + n) wait states; n = 1 a [23:0] d [15:0] wr wait address data external (3 + n) wait states; n = 1 tsys a [23:0] d [15:0] wr wait address data external (3 + n) wait states; n = 3 tsys a [23:0] d [15:0] wr wait TMP1962C10BXBG 2006-02-21 tmp1962-149 setting bit 3 (p33f) of the port 3 function register (p3fc) to 1 configures the wait input pin (p33) as the rdy input pin. the input supplied from the rdy pin to the external bus interface bl ock is the logical negation of the wait input. the bnw bit of the cs/wait control register (bmncs) defines the number of wait state cycles to be inserted. figure 8.13 through 8.15 show wait states inserted with the rdy input. figure 8.13 rdy input timing (with externally inserted (1 + n) wait states; n = 1) figure 8.14 rdy input timing (with externally inserted (3 + n) wait states; n = 1) 0 wait state external (1 + n) wait states; n = 1 address address data data tsys a [23:0] d [15:0] rd rdy external (3 + n) wait states; n = 1 tsys address data a [23:0] d [15:0] rd rdy TMP1962C10BXBG 2006-02-21 tmp1962-150 figure 8.15 rdy input timing (with externally inserted (3 + n) wait states; n = 3) (3) ale pulse width when the tmp1962 external buses are used in multiplexed bus mode, the ale pulse width can be programmed through the alesel bit of the syscr3 re gister within the cg. in separate bus mode, ale is not asserted but the value of the syscr3.alesel bit determines the time between an address being established and rd or wr being asserted. upon reset, alesel is set to 1, so that rd or wr is asserted two (internal) system clock cycles after an address is es tablished. clearing alesel to 0 causes rd or wr to be asserted one system clock cycle after an address is established. this setting applies to the whole external address space. figure 8.16 syscr3.alesel setti ng and external bus operation external (3 + n) wait states; n = 3 address data tsys a [23:0] d [15:0] rd rdy address address data data TMP1962C10BXBG 2006-02-21 tmp1962-151 (4) recovery time following an external bus cycle, a certain recovery time may be required before initiating the next external bus cycle. to allow for a recovery time, one or two dummy cycles can be inserted between back-to-back bus cycles. dummy cycles can be inserted eith er after a read cycle or a write cycle. dummy cycle insertion is programmable with the bnwcv (write recovery cycl e) and bnrcv (read recove ry cycle) bits of the cs/wait control register (bmncs). the number of dummy cycles (one or two internal system clock cycles) can be specified for each block. figure 8.17 shows timing with a recovery time inserted. figure 8.17 timing with a recovery time inserted tsys 1 recovery cycle address next address 2 recovery cycles cs a [23:0] rd wr tsys address next address cs a [23:0] rd wr no recovery cycle TMP1962C10BXBG 2006-02-21 tmp1962-152 8.4 external bus operati on (multiplexed bus mode) this section describes external bus operations. in the timing diagrams which follow, a23-a16 are used as the address bus, and ad15-ad0 are used as the address/data bus. (1) basic bus operation while the tmp1962 provides a total of three clock cycles to perform a read or write, it also allows the bus cycle to be extended by inserting wait states. the intern al system clock is also used as the basic clock for external bys cycles. figure 8.18 shows external bus read timing. figure 8.19 shows external bus write timing. while an on-chip address is being accessed, the external address bus maintains th e previous value with the ale pin kept inactive. during this time, the address/data bus assumes the high-impedan ce state, and bus control signals such as rd and wr remain inactive. figure 8.18 read cycle timing figure 8.19 write cycle timing tsys a [23:16] a d [15:0] a le rd external access internal access hi-z inactive inactive no change adr data csn a [23:16] a d [15:0] a le wr csn external access internal access hi-z inactive inactive no change adr data tsys TMP1962C10BXBG 2006-02-21 tmp1962-153 (2) wait timing the cs/wait controller provides three ways to insert wait states in a bus cycle for each address block: 1) inserting required number of wait state cy cles automatically (up to seven cycles) 2) using the wait pin to insert wait states dynamically (1+n, 3+n, 5+n or 7+n, where n is the number of wait stat e cycles inserted) 3) using the rdy pin to insert wait states dynamically (1+n, 3+n, 5+n or 7+n, where n is the number of wait state cycles inserted) the bnw bit of the cs/wait control register (bmncs ) defines the number of wait state cycles to be inserted automatically as well as external wait state input settings. figure 8.20 through 8.29 show bus cycle timings with wait states. figure 8.20 read cycle timing (with zero and one wait state) figure 8.21 read cycle timing (with five wait states) a [23:16] a d [15:0] a le rd wait state upper address upper address adr data adr data 0 wait state 1 wait state tsys a [23:16] a d [15:0] a le rd upper address adr data 5 wait states wait state tsys TMP1962C10BXBG 2006-02-21 tmp1962-154 figure 8.22 read cycle timing (wit h (1 + n) wait states; n = 1) figure 8.23 read cycle timing (wit h (3 + n) wait states; n = 1) figure 8.24 read cycle timing (wit h (3 + n) wait states; n = 3) a [23:16] a d [15:0] a le rd 0 wait state (1 + n) wait states; n = 1 wait wait upper address upper address adr data adr data wait state tsys a [23:16] a d [15:0] a le rd wait upper address adr data wait state (3 + n) wait states; n = 1 tsys a [23:16] a d [15:0] a le rd wait upper address adr data wait state (3 + n) wait states; n = 3 tsys TMP1962C10BXBG 2006-02-21 tmp1962-155 figure 8.25 write cycle timing (w ith zero and one wait state) figure 8.26 write cycle timi ng (with five wait states) a [23:16] a d [15:0] a le wr upper address upper address adr data adr data 0 wait state 1 wait state wait state tsys a [23:16] a d [15:0] a le wr upper address adr data 5 wait states wait state tsys TMP1962C10BXBG 2006-02-21 tmp1962-156 figure 8.27 write cycle timing (wit h (1 + n) wait states; n = 1) figure 8.28 write cycle timing (wit h (3 + n) wait states; n = 1) figure 8.29 write cycle timing (wit h (3 + n) wait states; n = 3) a [23:16] a d [15:0] a le wr wait upper address upper address adr data adr data 0 wait state (1 + n) wait states; n = 1 wait state ts y s a [23:16] a d [15:0] a le wr wait upper address adr data (3 + n) wait states; n = 1 wait state tsys a [23:16] a d [15:0] a le wr wait upper address adr data wait state (3 + n) wait states; n = 3 tsys TMP1962C10BXBG 2006-02-21 tmp1962-157 (3) ale pulse width the ale pulse width is programmed to 0.5 or 1.5 cl ock cycles through the al esel bit of the syscr3 register within the cg. the default is 1.5 cycles. th is setting applies to the whole external address space. figure 8.30 ale pulse width figure 8.31 shows read cycle timing, with the ale width programmed to 0.5 and 1.5 clock cycles. figure 8.31 read cycle timing (a le = 0.5 and 1.5 clock cycles) a le (alesel = 0) a d [15:0] (alesel = 1) a d [15:0] 0.5 clock cycles tsys 1.5 clock cycles a [23:16] a d [15:0] a le rd ale = 0.5 clock cycles ale = 1.5 clock cycles upper address adr data tsys upper address adr data note: in the tmp1962f10, configuring the ale pulse width as 0.5 or 1.5 clock cycles results in the actual ale pulse width being 1.5 or 2.5 clock cycles, respectively. TMP1962C10BXBG 2006-02-21 tmp1962-158 (4) recovery time following an external bus cycle, a certain recovery time may be required before initiating the next external bus cycle. to allow for a recovery time, one or two dummy cycles can be inserted between back-to-back bus cycles. dummy cycles can be inserted eith er after a read cycle or a write cycle. dummy cycle insertion is programmable with the bnwcv (write recovery cycl e) and bnrcv (read recove ry cycle) bits of the cs/wait control register (bmncs). the number of dummy cycles (one or two internal system clock cycles) can be specified for each block. figure 8.32 shows timing with a recovery time inserted. figure 8.32 timing with a recovery time inserted tsys tsys 1 recovery cycle address next address 2 recovery cycles address next address no recovery cycle cs a [23:0] rd wr cs a [23:0] rd wr TMP1962C10BXBG 2006-02-21 tmp1962-159 8.5 bus arbitration the tmp1962 provides support for an external bus master to take control of the external bus. two bus arbitration control signals, busrq and busak , are used to determine the bus master. one or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the tmp1962 internal bus. (1) bus access control external bus masters can gain cont rol of the external bus, but not the tmp1962 internal bus (g-bus). thus, external bus masters cannot access the tmp1962's on-chip memory and peripherals. the external bus interface (ebif) logic in the tmp1962 manages the arbitration of the external bus; the cpu and on-chip dmac do not participate in any way in this bus arbitration. during external bus mastership, the cpu and the on-chip dmac can access the internal me mory (ram and rom) and registers. once an external device assumes bus mastership, the cpu or the on-chip dmac has no way to regain the bus until the external bus master releases the bus. if the cpu or the on-chip dmac issues an external memory access request, it is forced to wait until the tmp1962 regains the bus. therefore, should busrq be left asserted for a long time, the tmp1 962 might suffer system lockups. (2) bus arbitration flow external devices capable of becoming bus masters assert busrq to request the bus. the tmp1962 samples busrq at the end of each external bus cycle, as seen on its internal bus (gbus). when the tmp1962 has made an internal decision to grant the bus, it asserts busak to indicate to the requesting device that the bus is available. at the same time, the tmp1962 puts the address bus, the data bus and bus control signals in the high-impedance state. a load or store may require multip le bus cycles, depending on the port size of the addressed device (dynamic bus sizing). in that case, the tmp1962 do es not grant the bus until the entire transfer is complete. the tmp1962, if so programmed, automatically inse rts dummy cycles between back-to-back bus cycles to allow for sufficient read recovery time. in dummy cycles, the tmp1962 has already internally initiated a bus cycle on the g-bus for the next external access. the tmp1962 can only accept an external bus request at the boundary of an intern al g-bus bus cycle. therefore, if busrq is asserted during a dummy cycle, the tmp1962 grants the bus after it completes the next external bus cycle. an external bus master must keep busrq asserted until it is granted the bus. a timing diagram of the bus arbitration sequence is shown in figure 8.33. TMP1962C10BXBG 2006-02-21 tmp1962-160 1) busrq is sampled high. 2) the tmp1962 recognizes the assertion of busrq . 3) the tmp1962 asserts busak at the completion of the current bus cycle. the external bus master recognizes busak and assumes bus mastership to start a bus transfer. figure 8.33 bus arbitration timing diagram (3) relinquishing the bus the external bus master relinquishes the bus when it has completed its bus transactions and no longer requires the bus. when the external bus master has comple ted its bus transactions, it de-asserts busrq to relinquish the bus to the tmp1962. figure 8.34 shows the timing for an external bus master to relinquish the bus. 1) the external bus master has control of the bus. 2) when the external bus master no longer needs the bus, it de-asserts busrq . 3) in response to the de-assertion of busrq , the tmp1962 de-asserts busak . figure 8.34 external bus master relinquishing the bus internal address external address (1) (2) (3) tmp1962 external access tmp1962 external access external bus master cycle tmp1962 external access tmp1962 external access tsys busrq busak internal address external address tmp1962 external tmp1962 external access tmp1962 external access external bus master cycle tmp1962 external access (1) (2)(3) tsys busrq busak TMP1962C10BXBG 2006-02-21 tmp1962-161 9. chip select/wait controller the tmp1962 supports direct connections to external devices (i/o devices, rom and sram). the tmp1962 provides four programmable chip select signals. programmable features include variable block sizes, data bus width, wait state insertion, and du mmy cycle insertion for ba ck-to-back bus cycles. 0cs - 3cs (multiplexed with p40-p43) are the chip select output pins for the cs0-cs3 address ranges. these chip select signals are generated when the cpu or on -chip dmac issues an address within the programmed ranges. the p40-p43 pins must be configured as cs0-cs3 by programming the port 4 control (p4cr) register and the port 4 function (p4fc) register. chip select address ranges are defined in terms of a base address and an address mask. there is a base/mask address (bman) register for each of the four chip select signals, wh ere n is a number from 0 to 3. there is also a set of three chip select/wait contro l registers, b01cs, b23cs and bexcs, each of which consists of a master enable bit, a data bus widt h bit, a wait state field and a dummy cycle field. external memory devices can also use the wait pin to insert wait states and consequently prolong read and write bus cycles. 9.1 programming chip select ranges each of the four chip select addre ss ranges is defined in the bman re gister. the basic chip select model allows one of the chip select output signals ( 0cs - 3cs ) to assert when an address on the address bus falls within a particular programmed range. the b01cs register defines specific operations for cs0 and cs1, and the b23cs register defines specific operations for cs2 and cs3 (see section 9.2). 9.1.1 base/mask address registers the organizations of the bman registers are shown in figure 9.1 and figure 9.2. the base address (ban) field specifies the starting address for a chip select. any set b it in the address mask field (man) masks the corresponding base address bit. the address mask field determines the block size of a particular chip select line. the address is compared on ev ery bus cycle. (1) base address the base address (ban) field specifi es the upper 16 bits (a31-a16) of the starting address for a chip select. the lower 16 bits (a15-a0) are assumed to be zero. thus, the base address is any multiple of 64 kbytes starting at 0x0000_0000. figure 9.3 shows the relationships between starting addresses and the bman values. (2) address mask the address mask (man) field defines whether any par ticular bits of the addr ess should be compared or masked. any set bit masks the corresponding ba se address bit. the address compare logic uses only the address bits that are not masked (i.e., mask bit cleared to 0) to de tect an address match. address bits that can be masked (i.e., supported block sizes) differ for the four chip select spaces as follows: cs0 and cs1 spaces: a29-a14 cs2 and cs3 spaces: a30-a15 note: use physical addresses in the bman registers. TMP1962C10BXBG 2006-02-21 tmp1962-162 base/mask address registers: bma0 (0xffff_e400) to bma3 (0xffff_e40c) 31 30 29 28 27 26 25 24 bma0 bit symbol ba0 (0xffff_e400) read/write r/w reset value 0 0 0 0 0 0 0 0 function a31-a24 of the starting address 23 22 21 20 19 18 17 16 bit symbol ba0 read/write r/w reset value 0 0 0 0 0 0 0 0 function a23-a16 of the starting address 15 14 13 12 11 10 9 8 bit symbol ma0 read/write r/w reset value 0 0 0 0 0 0 1 1 function must be written as 0. 7 6 5 4 3 2 1 0 bit symbol ma0 read/write r/w reset value 1 1 1 1 1 1 1 1 function cs0 block size 0: the addre ss compare logic uses this address bit. 31 30 29 28 27 26 25 24 bma1 bit symbol ba1 (0xffff_e404) read/write r/w reset value 0 0 0 0 0 0 0 0 function a31-a24 of the starting address 23 22 21 20 19 18 17 16 bit symbol ba1 read/write r/w reset value 0 0 0 0 0 0 0 0 function a23-a16 of the starting address 15 14 13 12 11 10 9 8 bit symbol ma1 read/write r/w reset value 0 0 0 0 0 0 1 1 function must be written as 0. 7 6 5 4 3 2 1 0 bit symbol ma1 read/write r/w reset value 1 1 1 1 1 1 1 1 function cs1 block size 0: the addre ss compare logic uses this address bit. figure 9.1 base/mask address registers (bma0 and bma1) note: bits 10-15 in the bma0 and bma1 must be written as zeros. the cs0 and cs1 block sizes can vary from 16 kbytes to 1 gbyte. however, the tmp1962 supports only 16 mbytes of external address space. therefore, bits 10-15 in the bma0 and bma1 must be cleared so that a24-a29 of an address will not be masked. TMP1962C10BXBG 2006-02-21 tmp1962-163 31 30 29 28 27 26 25 24 bma2 bit symbol ba2 (0xffff_e408) read/write r/w reset value 0 0 0 0 0 0 0 0 function a31-a24 of the starting address 23 22 21 20 19 18 17 16 bit symbol ba2 read/write r/w reset value 0 0 0 0 0 0 0 0 function a23-a16 of the starting address 15 14 13 12 11 10 9 8 bit symbol ma2 read/write r/w reset value 0 0 0 0 0 0 0 1 function must be written as 0. 7 6 5 4 3 2 1 0 bit symbol ma2 read/write r/w reset value 1 1 1 1 1 1 1 1 function cs2 block size 0: the addre ss compare logic uses this address bit. 31 30 29 28 27 26 25 24 bma3 bit symbol ba3 (0xffff_e40c) read/write r/w reset value 0 0 0 0 0 0 0 0 function a31-a24 of the starting address 23 22 21 20 19 18 17 16 bit symbol ba3 read/write r/w reset value 0 0 0 0 0 0 0 0 function a23-a16 of the starting address 15 14 13 12 11 10 9 8 bit symbol ma3 read/write r/w reset value 0 0 0 0 0 0 0 1 function must be written as 0. 7 6 5 4 3 2 1 0 bit symbol ma3 read/write r/w reset value 1 1 1 1 1 1 1 1 function cs3 block size 0: the addre ss compare logic uses this address bit. figure 9.2 base/mask address registers (bma2 and bma3) note: bits 9-15 in the bma2 and bma3 must be written as zeros. the cs2 and cs3 block sizes can vary from 32 kbytes to 2 gbytes. however, the tmp1962 supports only 16 mbytes of external address space. therefore, bits 9-15 in the bma2 and bma3 must be cleared so that a24-a30 of an address will not be masked. TMP1962C10BXBG 2006-02-21 tmp1962-164 starting address base address value (ban) 0xffff_0000 0xffff_ffff ffff a ddress 0x0000_0000 64 kbytes 0x0006_0000 0006 0x0005_0000 0005 0x0004_0000 0004 0x0003_0000 0003 0x0002_0000 0002 0x0001_0000 0001 0x0000_0000 0000 figure 9.3 relationships between starting a ddresses and base addres s register values 9.1.2 base address and address mask value calculations ? program the bma0 register as follows to cause cs 0 to be asserted in the 64 kbytes of address space starting at 0xc000_0000. 31 1615 0 ba0 ma0 1 10 0 0 0 0 0 0000000000000000 0 0 0 0 0 011 c 0 0 0 0 0 0 3 bma0 register value the ba0 field specifies the upper 16 bits of the starting address, or 0xc000. the ma0 field determines whether the a29-a14 bits of the address should be compared or masked. the a31 and a30 bits are always compared. bits 15-10 of the ma0 field must be cleared so th at the a29-a24 bits are always compared. when the bma0 register is programmed as show n above, the a31-a16 bits of the address are compared to the value of the ba0 field. cons equently, the 64-kbyte address range between 0xc000_0000 and 0xc000_ffff is defined as the 0cs space. TMP1962C10BXBG 2006-02-21 tmp1962-165 ? program the bma2 register as fo llows to cause cs2 to be asserted in the 1 mbyte of address space starting at 0x1fd0_0000. 31 1615 0 ba2 ma2 0 00 1 1 1 1 1 1101000000000000 0 0 0 1 1 111 1 f d 0 0 0 1 f bma2 register value the ba2 field specifies the upper 16 bits of the star ting address, or 0x1fd0. the ma2 field determines whether the a30-a15 bits of the address should be co mpared or masked. the a31 bit is always compared. bits 15-5 of the ma2 field must be cleared so that the a30-a20 bits are always compared. when the bma2 register is programmed as show n above, the a31-a20 bits of the address are compared to the value of the ba2 field. consequently, the 1-mbyte address range between 0x1fd0_0000 and 0x1fdf_ffff is defined as the cs2 space. upon reset, the cs0, cs1 and cs3 spaces are disabl ed while the cs2 space is enabled and spans the entire 4-gb address space. note: the tmp1962 does not assert any csn signal in the following address ranges: 0x1fc_0000 through 0x1fcf_ffff 0x4000_0000 through 0x400f_ffff 0xfffd_6000 through 0xfffd_ffff 0xffff_6000 through 0xffff_dfff TMP1962C10BXBG 2006-02-21 tmp1962-166 table 9.1 shows the programmable bl ock sizes for cs0 to cs3. even if the user has accidentally programmed more than one ch ip select line to the same area, only one chip select line is driven because of internal line priorities. cs0 has the highest priority, and cs3 the lowest. example: the starting address of the cs0 space is programmed as 0xc000_0000 with a size of 16 kbytes. the starting address of the cs1 space is programmed as 0xc000_0000 with a size of 64 kbytes. table 9.1 supported block sizes size (bytes) cs space 16 k 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m 16 m cs0 { { { { { { { { { { { cs1 { { { { { { { { { { { cs2 { { { { { { { { { { cs3 { { { { { { { { { { 0xc000_0000 0xc000_3fff 0xc000_0000 0xc000_3fff 0xc000_ffff cs1 space cs0 space when an attempt is made to access the overlapping area, the cs0 area is selected. TMP1962C10BXBG 2006-02-21 tmp1962-167 9.2 chip select/wait control registers the organization of the chip select/wait control registers is shown in figure 9.4. each of these registers consist of a master enable bit, a data bus width bit, a wait state field and a dummy cycle field. the b01cs register defines the cs0 and cs1 lines; the b23cs register defines the cs2 and cs3 lines; and the bexcs register defines the access characteristics for the rest of th e address locations. if the user has accidentally programmed more than one chip select line to th e same area, only one chip select line is driven because of in ternal line priorities (cs0 > cs1 > cs2 > cs3 > excs). b01cs (0xffff_e480), b23cs (0 xffff_e484), bexc s (0xffff_e488) 31 30 29 28 27 26 25 24 b01cs bit symbol b1wcv b1e b1rcv (0xffffe480) read/write r/w r/w r/w reset value 0 0 0 0 0 function number of dummy cycles (write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited cs1 enable 0: disable 1: enable number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited 23 22 21 20 19 18 17 16 bit symbol b1om b1bus b1w read/write r/w r/w reset value 0 0 0 0 1 0 1 function chip select output waveform 00: rom/ram do not use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles (automatically inserted wait states) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (externally inserted wait states) 1001: (1 + n) wait 1011: (3 + n) wait 1101: (5 + n) wait 1111: (7 + n) wait 1000,1010,1100,1110: reserved 15 14 13 12 11 10 9 8 bit symbol b0wcv b0e b0rcv read/write r/w r/w r/w reset value 0 0 0 0 0 function number of dummy cycles (write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited cs0 enable 0: disable 1: enable number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited 7 6 5 4 3 2 1 0 bit symbol b0om b0bus b0w read/write r/w r/w reset value 0 0 0 0 1 0 1 function chip select output waveform 00: rom/ram do not use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles (automatically inserted wait states) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (externally inserted wait states) 1001: (1 + n) wait 1011: (3 + n) wait 1101: (5 + n) wait 1111: (7 + n) wait 1000,1010,1100,1110: reserved figure 9.4 chip select/wait control registers (1/3) n ote:"please set the number of wait as "+1" when y ou use = lon g and busr q the ale width. " TMP1962C10BXBG 2006-02-21 tmp1962-168 31 30 29 28 27 26 25 24 b23cs bit symbol b3wcv b3e b3rcv (0xffff_e484) read/write r/w r/w r/w reset value 0 0 0 0 0 function number of dummy cycles (write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited cs3 enable 0: disable 1: enable number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited 23 22 21 20 19 18 17 16 bit symbol b3om b3bus b3w read/write r/w r/w reset value 0 0 0 0 1 0 1 function chip select output waveform 00: rom/ram do not use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles (automatically inserted wait states) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (externally inserted wait states) 1001: (1 + n) wait 1011: (3 + n) wait 1101: (5 + n) wait 1111: (7 + n) wait 1000,1010,1100,1110: reserved 15 14 13 12 11 10 9 8 bit symbol b2wcv b2e b2m b2rcv read/write r/w r/w reset value 0 0 1 0 0 0 function number of dummy cycles (write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited cs2 enable 0: disable 1: enable cs2 space select 0: whole 4-gbyte space 1: cs space number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited 7 6 5 4 3 2 1 0 bit symbol b2om b2bus b2w read/write r/w r/w reset value 0 0 0 0 1 0 1 function chip select output waveform 00: rom/ram do not use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles (automatically inserted wait states) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (externally inserted wait states) 1001: (1 + n) wait 1011: (3 + n) wait 1101: (5 + n) wait 1111: (7 + n) wait 1000,1010,1100,1110: reserved figure 9.4 chip select/wait control registers (2/3) n ote:"please set the number of wait as "+1" when y ou use = lon g and busr q the ale width. " TMP1962C10BXBG 2006-02-21 tmp1962-169 15 14 13 12 11 10 9 8 bexcs bit symbol bexwcv bexrcv (0xffff_e488) read/write r/w r/w r/w reset value 0 0 0 0 0 function number of dummy cycles (write recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: setting prohibited 7 6 5 4 3 2 1 0 bit symbol bexom bexbus bexw read/write r/w r/w reset value 0 0 0 0 1 0 1 function chip select output waveform 00: rom/ram do not use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles (automatically inserted wait states) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (externally inserted wait states) 1001: (1 + n) wait 1011: (3 + n) wait 1101: (5 + n) wait 1111: (7 + n) wait 1000,1010,1100,1110: reserved figure 9.4 chip select/wait control registers (3/3) both cs1 and cs2 are shared with port 4 pins. upon reset, all port 4 pins are configured as input port pins. to use them as chip select pins, set appropriate bits in the port 4 control (p4cr) register and the port 4 function (p4fc) register to 1. n ote:"please set the number of wait as "+1" when y ou use = lon g and busr q the ale width. " TMP1962C10BXBG 2006-02-21 tmp1962-170 10. dma controller (dmac) the tmp1962 contains an eight-channel dma controller. 10.1 features the tmp1962 dmac has th e following features: (1) eight independent dma channels (2) two types of bus requests, with and without bus snooping (3) transfer requests: internal transfer requests: software initiated external transfer requests: interrupt signals from on-chip i/o peripherals and external interrupt pins, or request signals from dreq pins request signals from dreq : level-sensitive mode (memory-to-memory) edge-triggered mode (memory-to-i/o, i/o-to-memory) (4) dual-address mode (5) memory-to-memory, memory-to-i/o, and i/o-to-memory transfers (6) transfer width: ? memory: 32-bit (8-bit and 16-bit memory devices are supported through the programming of the cs/wait controller.) ? i/o peripherals: 8-, 16-, and 32-bit (7) address pointers can increment, decrement or remain constant. the user can program the bit positions at which address increment or decrement occurs. (8) fixed channel priority (9) selectable endian mode TMP1962C10BXBG 2006-02-21 tmp1962-171 10.2 implementation 10.2.1 on-chip dmac interface figure 10.1 shows how the dmac is internally connected with the tx19 core processor and the interrupt controller (intc). figure 10.1 dmac connections within the tmp1962 the dmac provides eight independ ently programmable channels. w ith each dma channel, there are two associated signals: a dma request ( intdreqn ) and a dma acknowledge ( dackn ), where n is a channel number from 0 to 7. intdreqn is an input to the dmac coming from the intc, and dackn is an output signal from the dmac go ing to the intc. channels 2 and 3 also accept external dma requests from the 2dreq and 3dreq pins and send acknowledge signals through the 2dack and 3dack pins. channel priority is fixed. channel 0 has the highest priority, and channel 7 has the lowest priority. the tx19 core processor supports bus snooping. when snooping is enabled, the tx19 core processor grants the processor data bus to the dmac, so that the dmac can access the on-chip ram and rom connected to the processo r. snooping can be enabled and disabled under software control. the dmac bus snooping is discussed in section 10.2.3 in more detail. there are two bus request signals from the dmac going to the tx19 core processor, sreq and greq. greq is a bus request without snooping. sreq is a bus request with snooping. sreq always takes precedence over greq. tx19 core processor bus grant bus request bus release request bus grant acknowledge control address data busgnt * intdreq [7:0] * dack [7:0] * dmac interrupt controller (intc) (external requests) dreq [3:2] dack [3:2] busreq * busrel * haveit * external interrupt on-chip i/o peripheral interrupt requests * internal signals TMP1962C10BXBG 2006-02-21 tmp1962-172 10.2.2 dmac block the dmac block diagram is shown in figure 10.2. channel 3 channel 2 destination address register (darx) source address re g ister ( sarx ) b y te count re g ister ( bcrx ) channel control re g ister ( ccrx ) 31 0 channel 0 dma control register (dcr) data holding register (dhr) channel status re g ister ( csrx ) dma transfer control re g ister ( dtcrx ) request select register (rsr) (x = 0 to 7) channel 4 channel 5 channel 6 channel 7 channel 1 figure 10.2 dmac block diagram 10.2.3 bus snooping the tx19 core processor supports snoop operations. if snooping is enabled, the tx19 core processor grants the processor data bus to the dmac. because the dmac takes control of the processor data bus, the tx19 stops operating during snoop operations until the dmac relinquishes the bus to the processor. snooping allows the dmac to access the on-chip ram and rom, and thus to use them as a dma source or destination device. if snooping is disabled, the dmac cannot access the on-chip ram and rom. however, regardless of whether snooping is enabled or disabled, the dmac assumes mastership of the tmp1962 on-chip bus (g-bus) during dma transfers. therefore, as long as dma transfers are in progress, the tx19 core processor cannot access memory or i/o peripherals via the g-bus; any attempt to do so causes the processor pipeline to stall. note: if snooping is disabled, the tx19 core processor does not grant mastership of the processor data bus to the dmac. therefore, if the on-chip ram or rom is specified as a source or destination for dma transfers, a dma acknowledge signal will never be returned, causing bus lockup. TMP1962C10BXBG 2006-02-21 tmp1962-173 10.3 register description the dmac has fifty-one 32-bit registers. the dmac register map is shown in table 10.1. table 10.1 dmac registers (1/2) address symbol register name 0xffff_e200 ccr0 channel control register (ch. 0) 0xffff_e204 csr0 channel status register (ch. 0) 0xffff_e208 sar0 source address register (ch. 0) 0xffff_e20c dar0 destination address register (ch. 0) 0xffff_e210 bcr0 byte count register (ch. 0) 0xffff_e218 dtcr0 dma transfer control register (ch. 0) 0xffff_e220 ccr1 channel control register (ch. 1) 0xffff_e224 csr1 channel status register (ch. 1) 0xffff_e228 sar1 source address register (ch. 1) 0xffff_e22c dar1 destination address register (ch. 1) 0xffff_e230 bcr1 byte count register (ch. 1) 0xffff_e238 dtcr1 dma transfer control register (ch. 1) 0xffff_e240 ccr2 channel control register (ch. 2) 0xffff_e244 csr2 channel status register (ch. 2) 0xffff_e248 sar2 source address register (ch. 2) 0xffff_e24c dar2 destination address register (ch. 2) 0xffff_e250 bcr2 byte count register (ch. 2) 0xffff_e258 dtcr2 dma transfer control register (ch. 2) 0xffff_e260 ccr3 channel control register (ch. 3) 0xffff_e264 csr3 channel status register (ch. 3) 0xffff_e268 sar3 source address register (ch. 3) 0xffff_e26c dar3 destination address register (ch. 3) 0xffff_e270 bcr3 byte count register (ch. 3) 0xffff_e278 dtcr3 dma transfer control register (ch. 3) 0xffff_e280 ccr4 channel control register (ch. 4) 0xffff_e284 csr4 channel status register (ch. 4) 0xffff_e288 sar4 source address register (ch. 4) 0xffff_e28c dar4 destination address register (ch. 4) 0xffff_e290 bcr4 byte count register (ch. 4) 0xffff_e298 dtcr4 dma transfer control register (ch. 4) 0xffff_e2a0 ccr5 channel control register (ch. 5) 0xffff_e2a4 csr5 channel status register (ch. 5) 0xffff_e2a8 sar5 source address register (ch. 5) 0xffff_e2ac dar5 destination address register (ch. 5) 0xffff_e2b0 bcr5 byte count register (ch. 5) 0xffff_e2b8 dtcr5 dma transfer control register (ch. 5) 0xffff_e2c0 ccr6 channel control register (ch. 6) 0xffff_e2c4 csr6 channel status register (ch. 6) 0xffff_e2c8 sar6 source address register (ch. 6) 0xffff_e2cc dar6 destination address register (ch. 6) 0xffff_e2d0 bcr6 byte count register (ch. 6) 0xffff_e2d8 dtcr6 dma transfer control register (ch. 6) TMP1962C10BXBG 2006-02-21 tmp1962-174 figure 10.2 dmac registers (2/2) 0xffff_e2e0 ccr7 channel control register (ch. 7) 0xffff_e2e4 csr7 channel status register (ch. 7) 0xffff_e2e8 sar7 source address register (ch. 7) 0xffff_e2ec dar7 destination address register (ch. 7) 0xffff_e2f0 bcr7 byte count register (ch. 7) 0xffff_e2f8 dtcr7 dma transfer control register (ch. 7) 0xffff_e300 dcr dma control register (dmac) 0xffff_e304 rsr request select register (dmac) 0xffff_e30c dhr data holding register (dmac) TMP1962C10BXBG 2006-02-21 tmp1962-175 10.3.1 dma control register (dcr) 31 30 16 rstall w : read/write 15 7 0 rst7rst6 rst5 rst4 rst3 rst2 rst1 rst0 w : read/write bits mnemonic field name description 31 rstall reset all performs a software reset of the dmac. when the rstall bit is set to 1, all the dmac internal registers are initializ ed to their reset values. any transfer requests are remov ed and all the eight dma channels are put in idle state. 0: don't care 1: resets the dmac. 7 rst7 reset 7 performs a software reset of dmac channel 7. when the rst7 bit is set to 1, all the dmac channel 7 internal registers and the rsr channel 7 bit are initialized to their reset values. any transfer requests for channel 7 are removed and channel 7 is put in idle state. 0: don't care 1: resets dmac channel 7. 6 rst6 reset 6 performs a software reset of dmac channel 6. when the rst6 bit is set to 1, all the dmac channel 6 internal registers and the rsr channel 6 bit are initialized to their reset values. any transfer requests for channel 6 are removed and channel 6 is put in idle state. 0: don't care 1: resets dmac channel 6. 5 rst5 reset 5 performs a software reset of dmac channel 5. when the rst5 bit is set to 1, all the dmac channel 5 internal registers and the rsr channel 5 bit are initialized to their reset values. any transfer requests for channel 5 are removed and channel 5 is put in idle state. 0: don't care 1: resets dmac channel 5. 4 rst4 reset 4 performs a software reset of dmac channel 4. when the rst4 bit is set to 1, all the dmac channel 4 internal registers and the rsr channel 4 bit are initialized to their reset values. any transfer requests for channel 4 are removed and channel 4 is put in idle state. 0: don't care 1: resets dmac channel 4. 3 rst3 reset 3 performs a software reset of dmac channel 3. when the rst3 bit is set to 1, all the dmac channel 3 internal registers and the rsr channel 3 bit are initialized to their reset values. any transfer requests for channel 3 are removed and channel 3 is put in idle state. 0: don't care 1: resets dmac channel 3. TMP1962C10BXBG 2006-02-21 tmp1962-176 bits mnemonic field name description 2 rst2 reset 2 performs a software reset of dmac channel 2. when the rst2 bit is set to 1, all the dmac channel 2 internal registers and the rsr channel 2 bit are initialized to their reset values. any transfer requests for channel 2 are removed and channel 2 is put in idle state. 0: don't care 1: resets dmac channel 2. 1 rst1 reset 1 performs a software reset of dmac channel 1. when the rst1 bit is set to 1, all the dmac channel 1 internal registers and the rsr channel 1 bit are initialized to their reset values. any transfer requests for channel 1 are removed and channel 1 is put in idle state. 0: don't care 1: resets dmac channel 1. 0 rst0 reset 0 performs a software reset of dmac channel 0. when the rst0 bit is set to 1, all the dmac channel 0 internal registers and the rsr channel 0 bit are initialized to their reset values. any transfer requests for channel 0 are removed and channel 0 is put in idle state. 0: don't care 1: resets dmac channel 0. figure 10.3 dma control register (dcr) note 1: if the software reset command is written to the dcr register immediately after the completion of the last transfer cycle of a dma transaction, the dma-done interr upt will not be cleared. in this case, the software reset only initializes channel registers and other settings. note 2: do not issue a software reset command to the dcr register via a dma transfer. TMP1962C10BXBG 2006-02-21 tmp1962-177 10.3.2 channel control registers (ccrn) 31 30 25 24 23 22 21 20 19 18 17 16 str 0 ? nien abien ? ? ? ? big ? w w r/w r/w r/w r/w r/w r/w r/w r/w : read/write 1 1 1 0 0 0 1 0 : reset value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? exr pose lev sreq relen sio sac dio dac trsiz dps r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write 0 0 0 0 0 0 0 00 0 00 00 00 : reset value bits mnemonic field name description 31 str channel start start (reset value: -) enables a dma channel. setting thi s bit puts the dma channel in ready state. dma transfer starts as soon as a transfer request is received. only a write of 1 is valid, and a write of 0 has no effect on this bit. a 0 is returned on read. 1: enables a dma channel. 24 ? (reserved) this bit is re served and must be written as 0. 23 nien normal completion interrupt enable normal completion interrupt enable (reset value: 1) 1: enables an interrupt when the channel finishes a transfer without an error condition. 0: does not enable an interrupt when the channel finishes a transfer without an error condition. 22 abien abnormal termination interrupt enable abnormal completion interrupt enable (reset value: 1) 1: enables an interrupt when the channel encounters a transfer error. 0: does not enable an interrupt when the channel encounters a transfer error. 21 ? (reserved) this bit is reserved and reset to 1, but it must be written as 0. 20 ? (reserved) this bit is re served and must be written as 0. 19 ? (reserved) this bit is re served and must be written as 0. 18 ? (reserved) this bit is re served and must be written as 0. 17 big big-endian big e ndian (reset value: 1) 1: the dma channel operates in big-endian mode. 0: the dma channel operates in little-endian mode. 16 ? (reserved) this bit is re served and must be written as 0. 15 ? (reserved) this bit is re served and must be written as 0. 14 exr external request mode external request mode (reset value: 0) selects a transfer request mode. 1: external transfer requests (i nterrupt-driven or dreq-driven) 0: internal transfer reques ts (software-initiated) 13 pose positive edge positive edge (reset value: 0) defines the polarity of the interna l dma request signal (intdreqn or dreqn) for the channel. this bit is valid for external transfer requests (i.e., when exr = 1), and has no effect on internal transfer requests (i.e., when exr = 0). the po se bit must always be cleared because intdreqn and dreqn are low-active signals. 1: setting prohibited 0: intdreqn and dreqn are configured as falling-edge triggered or low-level sensitive. dackn is low active. figure 10.4 channel control registers (ccrn) (1/3) TMP1962C10BXBG 2006-02-21 tmp1962-178 bits mnemonic field name description 12 lev level mode level mode (reset value: 0) specifies whether external transfer requests are level-sensitive or edge-triggered. this bit is valid for external trans fer requests (i.e., when exr = 1), and has no effect on internal transfer requests (i.e., when exr = 0). the lev bit must always be set to 1 because intdreqn is low-active signal s. the lev bit determines how dreqn is recognized, as follows: 1: level mode. a specified level (if pose = 0, low level) of dreqn is recognized as a data transfer request. 0: edge mode. a specified transition (if pose = 0, falling edge) of dreqn is recognized as a data transfer request. 11 sreq snoop request snoop request (reset value: 0) controls whether or not to request bus mastership with snooping. if set, the tx19 core processor' s snoop function becomes valid, allowing the dmac to use the processor's data bus. if cleared, the snoop function is disabled. 1: the snoop function is enabled (i .e., sreq is used as a bus request signal). 0: the snoop function is disabled (i .e., greq is used as a bus request signal). 10 relen bus release request enable release request enable (reset value: 0) controls whether or not to respond to the bus release request signal from the tx19 core processor. this bit is valid when the dmac uses greq as a bus request signal. this bit has no meaning or effect when the dmac uses sreq as a bus request signal because, in that case, the tx19 core processor does not have the capability to generate a bus release request signal. 1: the dmac will respond to the bus release request signal from the tx19 core processor, if it has control of the bus. the dmac will relinquish the bus when the curre nt dma bus cycle completes. 0: the dmac will ignore the bus release request signal from the tx19 core processor. 9 sio i/o source source type: i/o (reset value: 0) specifies the type of the source device. 1: i/o device 0: memory 8 : 7 sac source address count sour ce address count (reset value: 00) selects the manner in which the source address changes after each cycle. 1x: fixed (remains unchanged) 01: decremented 00: incremented 6 dio i/o destination destination type: i/o (reset value: 0) specifies the type of the destination device. 1: i/o device 0: memory 5 : 4 dac destination address count destination address count (reset value: 00) selects the manner in which the destination address changes after each cycle. 1x: fixed (remains unchanged) 01: decremented 00: incremented figure 10.4 channel control registers (ccrn) (2/3) TMP1962C10BXBG 2006-02-21 tmp1962-179 bits mnemonic field name description 3 : 2 trsiz transfer size transfer size (reset value: 00) specifies the amount of data to be transferred in response to a dma request. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) 1 : 0 dps device port size device port size (reset value: 00) specifies the port size of a s ource or destination i/o device. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) figure 10.4 channel control registers (ccrn) (3/3) 10.3.3 request select register (rsr) 31 16 0 : read/write : reset value 15 3 2 0 0 reqs3 reqs2 r/wr/w : read/write 0 0 0 0 0 0 0 0 : reset value bits mnemonic field name description 3 reqs3 request select (ch. 3) request select (reset value: 0) selects the type of an external transfer request enabled for dma channel 3. 1: request from the dreq3 pin. 0: request from the interrupt controller (intc). 2 reqs2 request select (ch. 2) request select (reset value: 0) selects the type of an external transfer request enabled for dma channel 2. 1: request from the dreq2 pin. 0: request from the interrupt controller (intc). figure 10.5 request select register (rsr) note 1: the ccrn register must be programmed before placing the dmac in ready state. note 2: to access on-chip peripherals or to perform a dma transfer in response to a request issued through a dreq pin, the transfer size (trsiz) must be equal to the device port size (dps). note 3: the dps field has no meaning or effect on memory-to-memory transfers. note: bits 0, 1, and 4 to 7 of the rsr must be set to 0. TMP1962C10BXBG 2006-02-21 tmp1962-180 10.3.4 channel status registers (csrn) 31 23 22 21 20 19 18 17 16 act ncabc ? bes bed conf 00 r r/w r/w r/w r r r : read/write 0 0 0 0 0 0 0 : reset value 15 3 2 0 0 ? r/w : read/write 000 : reset value bits mnemonic field name description 31 act channel active channel active (reset value: 0) indicates whether or not the dm a channel is in ready state. 1: the dma channel is in ready state. 0: the dma channel is not in ready state. 23 nc normal completion normal completion (reset value: 0) if set, the dma channel has terminated by normal completion. if the nien bit in the ccrn is set, an interrupt is generated. the nc bit is cleared by writing a 0 to it. clearing the nc bit causes the interrupt to be cleared. the nc bit must be cleared prior to starting the next transfer. an attempt to set the str bit in the ccrn when nc = 1 will cause an error. a write of 1 has no effect on this bit. 1: the dma channel has terminated by normal completion. 0: the dma channel has not ter minated by normal completion. 22 abc abnormal completion abnormal completion (reset value: 0) if set, the dma channel has terminated with an error. if the abien bit in the ccrn is set, an interrupt is generated. the abc bit is cleared by writing a 0 to it. clearing the abc bit causes the interrupt to be cleared and the bes, bed and conf bits to be also cleared. the abc bit must be cleared prior to starting the next transfer. an attempt to set the str bit in the ccrn when abc = 1 will cause an error. a write of 1 has no effect on this bit. 1: the dma channel has terminated with an error. 0: the dma channel has not terminated with an error. 21 ? (reserved) this bit is re served and must be written as 0. 20 bes source bus error source bus error (reset value: 0) 1: a bus error has occurred during the source read cycle. 0: a bus error has not occurred during the source read cycle. 19 bed destination bus error destination bus error (reset value: 0) 1: a bus error has occurred during the destination write cycle. 0: a bus error has not occurred during the destination write cycle. 18 conf configuration error configuration error (reset value: 0) 1: a configuration error is present. 0: no configuration error is present. 2 : 0 ? (reserved) these bits are re served and must be written as 0s. figure 10.6 channel status registers (csrn) TMP1962C10BXBG 2006-02-21 tmp1962-181 10.3.5 source address registers (sarn) 31 16 saddr r/w : read/write ? : reset value 15 0 saddr r/w : read/write ? : reset value bits mnemonic field name description 31 : 0 saddr source address source address (reset value: -) contains the physical address of the source device. the address changes as programmed in the sac and trsiz fields in the ccrn and the sacm field in the dtcrn. figure 10.7 source addr ess registers (sarn) TMP1962C10BXBG 2006-02-21 tmp1962-182 10.3.6 destination address registers (darn) 31 16 daddr r/w : read/write ? : reset value 15 0 daddr r/w : read/write ? : reset value bits mnemonic field name description 31 : 0 daddr destination address de stination address (reset value: -) contains the physical address of the destination device. the address changes as programmed in the dac and trsiz fields in the ccrn and the dacm field in the dtcrn. figure 10.8 destination a ddress registers (darn) TMP1962C10BXBG 2006-02-21 tmp1962-183 10.3.7 byte count registers (bcrn) 31 24 23 16 0 bc r/w : read/write ? : reset value 15 0 bc r/w : read/write ? : reset value bits mnemonic field name description 23 : 0 bc byte count byte count (reset value: -) contains the number of bytes left to transfer on a dma channel. the count is decremented by 1, 2 or 4 (as determined by the trsiz field in the ccrn register) for each successful transfer. figure 10.9 byte count registers (bcrn) TMP1962C10BXBG 2006-02-21 tmp1962-184 10.3.8 dma transfer control registers (dtcrn) 31 16 0 : read/write : reset value 15 6 5 3 2 0 dacm sacm r/w : read/write 000 000 : reset value bits mnemonic field name description 5 : 3 dacm destination address count mode destination address count mode selects the manner in which the destination address is incremented or decremented. 000: counting begins with bit 0 of the darn. 001: counting begins with bit 4 of the darn. 010: counting begins with bit 8 of the darn. 011: counting begins with bit 12 of the darn. 100: counting begins with bit 16 of the darn. 101: reserved 110: reserved 111: reserved 2 : 0 sacm source address count mode source address count mode selects the manner in which the source address is incremented or decremented. 000: counting begins with bit 0 of the sarn. 001: counting begins with bit 4 of the sarn. 010: counting begins with bit 8 of the sarn. 011: counting begins with bit 12 of the sarn. 100: counting begins with bit 16 of the sarn. 101: reserved 110: reserved 111: reserved figure 10.10 dma transfer control registers (dtcrn) TMP1962C10BXBG 2006-02-21 tmp1962-185 10.3.9 data holding register (dhr) 31 16 dot r/w : read/write ? : reset value 15 0 dot r/w : read/write ? : reset value bits mnemonic field name description 31 : 0 dot data on transfer data on transfer (reset value: -) contains data read from the source address during a dual-address operation. figure 10.11 data holding register (dhr) TMP1962C10BXBG 2006-02-21 tmp1962-186 10.4 operation this section describes the operation of the dmac. 10.4.1 overview the dmac is a high-speed 32-bit dma controller used to move quickly large blocks of data between i/o peripherals and memory without intervention of the tx19 core processor. (1) devices supported for the source and destination the dmac handles data transfers from memory to memory, and between memory and i/o peripherals. the device from which data is transferre d is referred to as a source device, and the device to which data is transferred is referred to as a destination device. both memory and i/o peripherals can be a source or destination device. the dmac supports data transfers from memory to i/o peripherals, from i/o peripherals to memory , and from memory to memory, but not from i/o peripherals to i/o peripherals. dma protocols for memory and i/o peripherals differ in that when accessing an i/o peripheral, the dmac asserts the dackn (n = channel number) signal to indicate that data is being transferred in response to a previous transfer reque st. because each dma channel has only one dackn signal, the dmac cannot handle data transf ers between two i/o peripherals. interrupt requests can be programmed to be a trig ger to initiate a dma process instead of requesting an interrupt to the tx19 core processor. if so programmed, the interrupt controller (intc) forwards a dma request to the dmac (see "i nterrupts"). the dma request co ming from the intc is cleared when the intc receives a dackn from the dmac. consequently, a dma request for a transfer to/from an i/o peripheral is cleared after each dma bus cycle (i.e., every time the number of bytes programmed into the ccrn.trsiz field is transferred). on the other hand, during memory-to-memory transfer, the dackn signal is not asserted until the byte count register (bcrn) reaches zero. therefore, memory-to-memory transfer can continuously move large blocks of data in response to a single dma request. for example, data transfers between the tmp1962 on -chip peripheral and on- or off-chip memory is discontinued after every dma bus cycle. nonetheless, until the bcrn register reaches zero, the dmac remains in ready state to wait for the next transfer request. (2) exchanging bus mastership (bus arbitration) in response to a dma request, the dmac issues a bu s request to the tx19 core processor. when the dmac receives a bus grant signal from the tx19 core processor, it assumes bus mastership to service the dma request. there are two bus request signals from the dmac going to the tx19 core processor. one is a bus request without snooping (greq), and the other is a bus request with snooping (sreq). the sreq bit in the ccrn register is used to select a bu s request signal to use for each dma channel. while the dmac has control of the bus, the tx19 co re processor may issue a bus release request to the dmac. the relen bit of the ccrn register controls whether to honor this request on a channel-by-channel basis. this setting has a meaning only when a dma channel uses greq (i.e., a bus request without snooping). it has no meaning or effect when a dma channel uses sreq (i.e., a bus request with snooping) because, in this case, the tx19 core processor does not have the capability to generate a bus release request. TMP1962C10BXBG 2006-02-21 tmp1962-187 the dmac relinquishes the bus to the tx19 core processor when there is no pending dma request to be serviced. (3) transfer request generation each dma channel supports two types of request generation method: internal and external. internal requests are those generated within the dmac. the dm a channel is started as soon as the str bit in the ccrn register is set. the channel immediately requests the bus and begins transferring data. if a channel is programmed for external request and the str bit is set, the intdreqn signal asserted by the interrupt controller or the dreqn signal asserted by the external device causes the channel to request the bus and begin a transfer. the dmac can be programmed to recognize a transfer request either with the low level of the intdreqn signal or with the falling edge or low level of the dreqn signal. (4) data transfer modes the tmp1962 dmac supports dual-address tran sfers, but not single-address transfers. the dual-address mode allows data to be transferred from memory to memory and between memory and an i/o peripheral. in this mode, the dmac explicitly addresses both the source and destination devices. the dmac also generates a dackn signal when accessing an i/o peripheral. in dual-address mode, a transfer takes place in two dma bus cycles: a source read cycle and a destination write cycle. in the source read cycle, the data being transferred is read from the source address and put into the dmac internal data holdin g register (dhr). in the destination write cycle, the dmac writes data in the dhr to a destination address. (5) dma channel operation the dmac has eight independent dma channels, 0 to 7. setting the start (str) bit in the ccrn (n = 0-7) enables a particular channe l and puts it in ready state. when a dma request is detected in any of the channels in ready state, the dmac arbitrates for the bus and begins a transfer. when no dma request is pending, the dmac relinquishes the bus to the tx19 core processor and returns to ready state. the channel can te rminate by normal completion or from an error of a bus cycle. when a channel terminat es, that channel is put in idle state. interrupts can be generated by error termination or by normal channel termination. figure 10.12 shows general state transitions of a dma channel. figure 10.12 dma channel state transitions note 1: the nmi interrupt is left pending while the dmac has control of the bus. note 2: do not place the tmp1962 in halt power-down mode while the dmac is operating. start transfer done idle ready transfer the dmac assumes bus mastership. the dmac gives up bus mastership. the dmac gives up bus mastership. the dmac assumes bus mastership. TMP1962C10BXBG 2006-02-21 tmp1962-188 (6) summary of transfer modes the dmac can perform data transfers as follow s according to the combination of mode settings. transfer request edge/level address mode data flow internal ? memory-to-memory memory-to-memory memory-to-i/o external low level ( intdreqn ) i/o-to-memory low level ( dreqn ) memory-to-memory memory-to-i/o external falling edge ( dreqn ) dual i/o-to-memory (7) address change options address pointers can increment, decrement or re main constant. the sac and dac fields in the ccrn respectively select address change directions for the source address register (sarn) and the destination address register (darn). while memory addresses can be programmed to increment, decrement or remain constant, i/o addresses must be programmed to remain constant. when an i/o peripheral is selected as the source or destination device, the sac or dac field in the ccrn must be set to 1x (address fixed). the sacm and dacm fields in the dtcrn provide options to program bit positions at which the source and destination addresses are incremented or decremented after each tr ansfer. the bit position can be bit 0, 4, 8, 12 or 16. use of bit 0 is the regular increment/d ecrement mode in which the address changes by 1, 2 or 4, according to the source or destination size. two examples of how other increment/decrement modes affect ad dress changes are shown below. example 1: when address bit 0 is selected in the sacm field and address bit 4 is selected in the dacm field sac: programmed to increment the source address dac: programmed to increment the destination address trsiz: programmed to a transfer size of 32 bits source address: 0xa000_1000 destination address: 0xb000_0000 sacm: 000 bit 0 is the source address bit at which address increment occurs. dacm: 001 bit 4 is the destination address bi t at which address increment occurs. source destination 1st transfer 0xa000_1000 0xb000_0000 2nd transfer 0xa000_1001 0xb000_0010 3rd transfer 0xa000_1002 0xb000_0020 4th transfer 0xa000_1003 0xb000_0030 ? ? TMP1962C10BXBG 2006-02-21 tmp1962-189 example 2: when address bit 8 is selected in the sacm field and address bit 0 is selected in the dacm field sac: programmed to decrement the address dac: programmed to decrement the address trsiz: programmed to a transfer size of 16 bits source address: 0xa000_1000 destination address: 0xb000_0000 sacm: 010 bit 8 is the source address bit at which address decrement occurs. dacm: 000 bit 0 is the destination address bi t at which address decrement occurs. source destination 1st transfer 0xa000_1000 0xb000_0000 2nd transfer 0x9fff_ff00 0xafff_fffe 3rd transfer 0x9fff_fe00 0xafff_fffc 4th transfer 0x9fff_fd00 0xafff_fffa ? ? 10.4.2 transfer request generation a dma request must be issued for the dmac to initiate a data transfer. each dma channel in the dmac supports two types of request generation method: internal and external. in either request generation mode, once a dma channel is started, a dm a request causes the dmac to arbitrate for the bus and begin transferring data. ? internal request generation a channel is programmed for internal request by clearing the exr bit in the ccrn. in internal request generation mode, a transfer request is genera ted as soon as the str bit in the ccrn is set. an internally generated request keeps a transfer request pending until the transfer is complete. if no transition to a higher-priority dma channe l or a bus master occurs, the channel will use 100% of the available bus bandwidth to transfer all data continuously. internally generated requests support only memory-to-memory transfer. ? external request generation a channel is programmed for external request by setting the exr bit in the ccrn. in external request generation mode, setting the str bit in the ccrn puts the channel in ready state. while in ready state, assertion of the intdreqn signal (where n is the channel number) coming from the interrupt controller (intc), or the dreqn signal coming from an external device, causes a transfer request to be generated. extern ally generated requests support data transfers from memory to memory and between memory and an i/o peripheral. the tmp1962 can recognize a transfer request with the low level of intdreqn or the falling edge or low level of dreqn . the transfer size, i.e., the amount of data to be transferred in response to a transfer request, is programmed in the trsiz field in the ccrn. the transfer size can be 32 bits, 16 bits or 8 bits. details of transfer request generation by intdreqn and dreqn are described below. TMP1962C10BXBG 2006-02-21 tmp1962-190 (1) transfer request coming from the intc a transfer request is removed by assertion of the dackn signal (where n is the channel number). dackn is asserted: 1) when an i/o peripheral bus cy cle has completed, and 2) when the byte count register (bcrn) has reached zero in memory-to-me mory transfer. consequently, a memory-to-i/o or i/o-to-memory transfer request terminates after one dma bus cycle completes, whereas memory-to-memory transfer can continuously move large blocks of data in response to a single dma request. the intc might clear intdreqn before the dmac accepts it and begins a data transfer. it must be noted that, even if that happens, a dma bus cycle might be executed after the interrupt request has been cleared. (2) transfer request coming from an external device in edge mode, each transfer request requi res the deassertion and assertion of the dreqn signal to produce an effective edge. in level mode, a contin uous transfer request can be made by holding an effective level. memory-to-memory transfer supports low level-sensitive mode only. i/o-to-memory transfer supports falling edge-sensitive mode only. ? level mode in level mode, the dmac samples the dreqn signal on the rising edge of the internal system clock. if dreqn is sampled low when the corresponding channel is in ready state, the dmac starts transferring data. to detect the low level of dreqn , clear the pose bit (bit 13) of the ccrn register to 0. the dackn signal is also low active. once the external device has asserted dreqn , it must be held low until dackn is asserted. if dreqn is deasserted before dackn is asserted, the dmac may not recognize the transfer request. if dreqn is not sampled low, the dmac assumes th at there is no transfer request for the channel and starts transferring data for another channel or relinquishes the bus, entering ready state. the quantity of data transferred w ith a single transfer request is specified in the trsiz field (bits 3 and 2) of the ccrn register. figure 10.13 transfer request timing (level mode) dreqn a [31:1] dackn data transfer TMP1962C10BXBG 2006-02-21 tmp1962-191 ? edge mode in edge mode, the dmac is driven by the falling edge of the dreqn signal. if the dmac detects the falling edge of dreqn on the rising edge of the internal system clock (samples dreqn high on the previous system clock edge and low on the current edge) when the corresponding channel is in read y state, the dmac assumes that there is a transfer request on the channel and starts transferring data. to det ect the falling edge of dreqn, clear the pose bit (bit 13) and lev bit (bit 12) of the ccrn regist er to 0. the dackn signal is low active. after asserting the dackn signal, the dmac tran sfers next data if it detects another falling edge of dreqn. if the dmac does not detect a falling edge of dreqn after asserting dackn, it assumes that there is no transfer request for th e channel and starts transferring data for another channel or relinquishes the bu s, entering ready state. the quantity of data transferred w ith a single transfer request is specified in the trsiz field (bits 3 and 2) of the ccrn register. figure 10.14 transfer request timing (edge mode) dreqn a[ 31:1] dackn data transfer data transfer TMP1962C10BXBG 2006-02-21 tmp1962-192 10.4.3 dma address modes dma transfer is generally performed in either of two address modes: dual-address mode and single-address mode. in dual-address mode, both the source and destination devices are explicitly addressed. in single-address mode, only either the source device or the destination device is explicitly addressed. the tmp1962, however, supports dual-address mode only. in dual-address mode, two bus transfers occur: a read from the source device, and a write to the destination device. in the source read cycle, data is read from the source addres s and placed in the dmac internal data holding register (dhr). then, in the destination write cycle, the data held in the dhr is written to the destination address. figure 10.15 dual-address transfer mode the transfer size programmed into the ccrn.trsiz field determines the amount of data that is transferred from a source device to a destination devi ce in response to a dma request. the transfer size can be 32 bits, 16 bits or 8 bits. the internal dhr is a 32-bit register that serves as a buffer for the data being transferred from a source device to a destination device during dual-address mode. memory accesses occur in a manner to fulfill the ccrn.trsiz setting. remember that the cs/wait controller supports either 16-bit or 8-bit bus accesses for external memory. if the dma transfer size is programmed to 32 bits in ccrn.trsiz, dma read and write cycles each take up to four bus cycles to complete. a 16-bit data bus, as programmed in the cs/wait controller, requires two independent bus cycles to complete a 32-bit transfer. likewise, an 8-bit data bus requires four independent bus cycles to complete a 32-bit transfer. dmac destination device data data bus (1) address (2) (2) (1) address bus source device TMP1962C10BXBG 2006-02-21 tmp1962-193 memory-to-i/o and i/o-to-memory dma transfers are governed by the setting of the ccrn.dps field in addition to the setting of ccrn.trsiz. the dps field defines the port size of a source or destination i/o peripheral. the i/o port size can be 32 bits, 16 bits or 8 bits. if the transfer size is equal to the i/o port size, an i/o access takes a single read or single write cycle. if the i/o port size is less than the programmed transfer size, the internal 32-bit dh r serves as a buffer for the data being transferred. for example, assume that the transfer size is programmed to 32 bits. if the source i/o port size is 8 bits and the destination memory width is 32 bits, then four 8-bit read cycles occur, followed by a 32-bit write cycle. (if the destination is an external memory with a 16-bit data bus, the write cycle takes two bus cycles.) the 32 bits of data ar e buffered in the dhr until the destination write cycle occurs. source and destination addresses can be programmed to increment or decrem ent after each transfer. the sarn and darn change, if so pr ogrammed, after each data transfer, depending on the transfer size, i.e., the programmed trsiz value. the brcn is d ecremented by trsiz for each data transfer. it is forbidden to program the device port size (dps) to a va lue greater than the dma transfer size (trsiz). the relationships between trsiz and dps are summarized below. table 10.2 dma transfer sizes and device port sizes (in dual-address mode) trsiz dps number of i/o bus cycles 0x (32 bits) 0x (32 bits) 1 0x (32 bits) 10 (16 bits) 2 0x (32 bits) 11 (8 bits) 4 10 (16 bits) 0x (32 bits) setting prohibited 10 (16 bits) 10 (16 bits) 1 10 (16 bits) 11 (8 bits) 2 11 (8 bits) 0x (32 bits) setting prohibited 11 (8 bits) 10 (16 bi ts) setting prohibited 11 (8 bits) 11 (8 bits) 1 TMP1962C10BXBG 2006-02-21 tmp1962-194 10.4.4 dma channel operation each dma channel is started by setting the str bit in the ccrn to 1. once started, the dmac checks the channel setups for configuration errors. if no conf iguration error is present, the channel enters ready state. when a dma request is detected while in ready st ate, the dmac arbitrates for the bus and begins transferring data. the channel can terminate by normal completion or from an error. the state of termination is indicated in the csrn. channel startup a dma channel is started by setting the str bit in the ccrn. once started, the dmac checks the channel setups for configuration errors. if a configuration error is detected, the channel terminates abnormally. if no configuration error is present, the channel enters ready state. once a channel enters ready state, the act bit in the csrn is set to 1. if the channel is programmed for internal reques ts, the channel requests the bus and starts transferring data immediately. if the cha nnel is programmed for external requests, intdreqn or dreqn must be asserted before the channel requests the bus. channel termination a dma channel can terminate by normal completio n or from an error. the status of a dma operation can be determined by reading the csrn. a channel terminates abnormally if an attempt is made to set the str bit in the ccrn when the nc or abc bit in the csrn is set. normal termination a dma channel terminates by normal completion in the following case. normal completion always occurs at the boundary of transfers pr ogrammed into the ccrn.trsize field. ? data transfers have terminated, with the bcrn decremented to 0. abnormal termination the paragraphs that follow summari ze the cases in which a dma channe l terminates from an error. ? configuration errors a configuration error results when the channel initialization contains inconsistencies or errors. a configuration error is reported before any data transfer takes place; therefore, in case of a configuration error, the sarn, darn and bcrn remain unaltered. when a dma channel has terminated from a configuration error, the abc and conf bits in the csrn are set. a configuration error occurs for the following cases: ? both the ccrn.sio and ccrn.dio bits are set. ? the ccrn.str bit is set when the nc or abc bit in the csrn is set. TMP1962C10BXBG 2006-02-21 tmp1962-195 ? the bcrn contains a value that is not an integer multiple of the transfer size programmed into the ccrn.trsiz field. ? the sarn or darn contains a value that is not an integer multiple of the transfer size programmed into th e ccrn.trsiz field. ? the ccrn.trsiz and ccrn.dps fields contain illegal combinations. ? the ccrn.str bit is set when the bcrn contains a value of zero. ? bus errors when a dma channel has terminat ed from a bus error, the abc bit and the bes or bed bit in the csrn are set. ? a bus error has been reported during a source read or destination write cycle. 10.4.5 dma channel priority the dmac provides a fixed priority for the eight channels, with channel 0 always having the highest priority and channel 7 the lowest. for example, when transfer requests occur on channels 0 and 1 simultaneously, the channel 0 request is serviced first. the channel 1 request is left pending. so that the channel 1 request is serviced, it must be maintained until data transfer complete s on channel 0. remember that the internally generated request is kept until the se rvicing of the request is finished. external transfer requests come from the interrupt controller (intc). th e intc can program any interrupts to be used as a dma trigger instead of as an interrupt request. if such an interrupt is programmed for edge sensitivity, the intc internally maintains a transfer request. however, a level-sensitive interrupt is not held in the intc; thus the interrupt request signal must remain asse rted until the servicing of the dma request begins. a higher-priority channel always gets the attenti on of the dmac. if a transfer request occurs on channel 0 while a request on channel 1 is being serviced, the servicing of the channel 1 request is suspended temporarily in order to service the channel 0 request first. after the channel 0 request has been serviced, channel 1 resumes the remaining data transfer. channel transitions take place at the boundary of a transfer size programmed for the current channel being serviced; that is, after all data in the dhr are written to a destination. interrupts the dmac can generate an interrupt request (i ntdman) to the tx19 core processor upon the completion of a channel operation: either by normal channel termination or by abnormal termination of a bus cycle. ? normal completion interrupt when a channel operation terminates by normal completion, the nc bit in the csrn is set to 1. at this time, if the nien bit in the ccrn is se t, an interrupt request is generated to the tx19 core processor. ? abnormal completion interrupt when a channel operation terminates abnormally, the abc bit in the csrn register is set to 1. at this time, if the abien bit in the ccrn register is set, an interrupt request is generated to the tx19 core processor. note: the contents of the bcrn, sarn and darn are not guaranteed when a channel has terminated due to a bus error. chapter 20 lists the reserved addresses that, if accessed, cause a bus error. TMP1962C10BXBG 2006-02-21 tmp1962-196 10.5 dma transfer timing all dmac operations are synchronous to the rising edges of the internal system clock. 10.5.1 dual-address mode ? memory-to-memory transfer figure 10.16 shows a dma cycle from one external 16-bit memory to another, with the transfer size programmed to 16 bits. a block of data is transferred until the bcrn register reaches 0. figure 10.16 memory-to-memory transfer (dual-address mode) ? memory-to-i/o transfer figure 10.17 shows a dma cycle from a 16-bit me mory to an 8-bit i/o peripheral, with the transfer size progra mmed to 16 bits. figure 10.17 memory-to-i/o transfer (dual-address mode) a [23:0] 0cs rd wr / hwr d [15:0] read write data data 1cs tsys a [23:0] 0cs rd wr d [15:0] read write data data 1cs write data tsys TMP1962C10BXBG 2006-02-21 tmp1962-197 ? i/o-to-memory transfer figure 10.18 shows a dma cycle from an 8-bit i/o peripheral to a 16-bit memory, with the transfer size progra mmed to 16 bits. figure 10.18 i/o-to-memory tr ansfer (dual-address mode) a [23:0] 0cs rd wr / hwr d [15:0] read read data 1cs write data data tsys TMP1962C10BXBG 2006-02-21 tmp1962-198 10.5.2 transfer mode responded to dreqn ? transfer from the on-chip ram to an external memory (multiplex bus, 5 waits insertion, level mode) figure 10.19 shows two dma cycles from the on-chip ram to a 16-bit external memory, with the transfer size programmed to 16 bits. figure 10.19 level mode (transfer from t he on-chip ram to an external memory) ? transfer from an external memory to the on-chip ram (multiplex bus, 5 waits insertion, level mode) figure 10.20 shows two dma cycles from a 16-b it external memory to the on-chip ram, with the transfer size programmed to 16 bits. figure 10.20 level mode (transfer from an external memory to the on-chip ram) internal system clock dreqn dackn a le a [23:16] a d [15:0] rd wr hwr csn w/r add add add data data (7 + ) clock 5 waits dreqn dackn a le a [23:16] a d [15:0] rd wr hwr csn w/r add add add data data (7 + ) clock 5 waits internal system clock TMP1962C10BXBG 2006-02-21 tmp1962-199 ? transfer from the on-chip ram to an external memory (separate bus, 5 waits insertion, level mode) figure 10.21 shows two dma cycles from the on-chip ram to a 16-bit external memory, with the transfer size programmed to 16 bits. figure 10.21 level mode (transfer from t he on-chip ram to an external memory) ? transfer from an external memo ry to the on-chip ram (separat e bus, 5 waits insertion, level mode) figure 10.22 shows two dma cycles from a 16-b it external memory to the on-chip ram, with the transfer size programmed to 16 bits. figure 10.22 level mode (transfer from an external memory to the on-chip ram) internal system clock dreqn dackn a [23:0] d [15:0] rd wr hwr csn w/r a dd data data (7 + ) clock 5 waits a dd data data (7 + ) clock 5 waits dreqn dackn a [23:0] d [15:0] rd wr hwr csn w/r internal system clock TMP1962C10BXBG 2006-02-21 tmp1962-200 ? transfer from the on-chip ram to an external memory (multiplex bus, 5 waits insertion, edge mode) figure 10.23 shows a dma cycle from the on-chi p ram to a 16-bit external memory, with the transfer size progra mmed to 16 bits. figure 10.23 edge mode (transfer from t he on-chip ram to an external memory) ? transfer from an external memory to the on-c hip ram (multiplex bus, 5 waits insertion, edge mode) figure 10.24 shows a dma cycle from a 16-bit ex ternal memory to the on-chip ram, with the transfer size progra mmed to 16 bits. figure 10.24 edge mode (transfer from an external memory to the on-chip ram) a dd a dd data (7 + ) clock 5 waits internal system clock dackn a [23:16] a d [15:0] rd wr hwr csn w/r dreqn a le a dd a dd data (7 + ) clock 5 waits internal system clock dackn a [23:16] a d [15:0] rd wr hwr csn w/r dreqn a le TMP1962C10BXBG 2006-02-21 tmp1962-201 ? transfer from the on-chip ram to an external memory (separate bus, 5 waits insertion, edge mode) figure 10.25 shows a dma cycle from the on-chi p ram to a 16-bit external memory, with the transfer size progra mmed to 16 bits. figure 10.25 edge mode (transfer from t he on-chip ram to an external memory) ? transfer from an external memory to the on-chip ram (separate bus, 5 waits insertion, edge mode) figure 10.26 shows a dma cycle from a 16-bit ex ternal memory to the on-chip ram, with the transfer size progra mmed to 16 bits. figure 10.26 edge mode (transfer from an external memory to the on-chip ram) a dd data (7 + ) clock 5 waits internal system clock dackn a [23:0] d [15:0] rd wr hwr csn w/r dreqn a dd data (7 + ) clock 5 waits internal system c lock dackn a [23:0] d [15:0] rd wr hwr csn w/r dreqn TMP1962C10BXBG 2006-02-21 tmp1962-202 10.6 programming example the following illustrates th e programming required to transfer data from an sio receive buffer (scnbuf) to the on-chip ram. (1) dmac settings: ? dma channel used: channel 0 ? source address: sc1buf ? destination address: 0xffff _9800 (physical address) ? number of bytes transferred: 256 (2) sio settings: ? data format: 8 bits, uart ? sio channel used: channel 1 ? transfer rate: 9600 bps dma channel 0 is used for the transfer. the sio1 recei ve interrupt is used as a trigger to start the dma channel. (3) dma channel 0 settings: dcr 0x8000_0000 / * reset dmac * / imcd 31 23 xxxx, xxxx, xx10, x100 / * interrupt level = 4 (arbitrary) * / intclr 0x36 /* ivr[9:4] * / dtcr0 0x0000_0000 / * dacm = 000 * / / * sacm = 000 * / sar0 0xffff_f208 / * physical address of sc1buf * / dar0 0xffff_9800 / * physical address of destination * / bcr0 0x0000_00ff / * 256 (number of bytes to be transferred) / ccr0 0x80c0_5b0f (contents) 31 27 23 19 1 0 0 0 000011000000 15 11 7 3 0 1 0 1 1 x 1 1 x 0 0 0 1 1 1 1 (4) sio channel 1 settings: imc4 31 23 xxxx, xxxx, xx11, 1000 / * use intrx1 as a dma trigger and select dma ch. 0 * / intclr 0x12 /* ivr[9:4]; clear intrx1 * / sc1mod0 0x29 /* uart mode, 8-bit data format, baud rate generator * / sc1cr 0x00 br1cr 0x1f / * @fc = 40.5 mhz (approx. 1.05 mbps) * / TMP1962C10BXBG 2006-02-21 tmp1962-203 11. 8-bit timers (tmras) the tmp1962 has a twelve-channel 8-bit timer (tmra0-tmrab), which is comprised of six modules named tmra01, tmra23, tmra45, tmra67, tmra89 and tmraab. the tmra01 contains the tmra0 and the tmra1, the tmra23 contains the tmra2 and tmra3, and so on. each timer module has the following operating modes: ? 8/16/24/32-bit interval timer mode ? 8-bit programmable pulse generation (ppg) mode (variable frequency, variable duty cycle) ? 8-bit pulse width modulated (pwm) signal generation mode (fixed frequency, variable duty cycle) figure 11.1 is a block diagram of the tmra01. the main components of a timer channel are an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. two timer channels share a prescaler and a timer flip-flop. a total of eight registers provide control over the operating modes and timer flip-flops for each timer module. the six modules are functionally equivalent and can be independently programmed. in the following sections, any references to the tmra01 also apply to the other modules. table 11.1 gives the pins and registers for the six timer modules. table 11.1 pins and registers for tmras (1/3) module specifications tmra01 tmra23 external clock input ta0in (shared with pa0) ta2in (shared with pa2) external pins timer flip-flop output ta1out (shared with pa1) ta3out (shared with pa3) timer run register ta01run (0x ffff_f103) ta23run (0xffff_f10b) timer control register ta01cr (0xffff_f102) ta23cr (0xffff_f10a) timer registers ta0reg (0xffff_f101) ta1reg (0xffff_f100) ta2reg (0xffff_f109) ta3reg (0xffff_f108) timer mode register ta01mod (0xffff_f107) ta23mod (0x ffff_f10f) timer flip-flop control register ta1ffcr (0xffff_f106) ta3ffcr (0xffff_f10e) timer interrupt mask register tag0im (0xffff_f105) registers (addresses) timer interrupt status register tag0st (0xffff_f104) TMP1962C10BXBG 2006-02-21 tmp1962-204 table 11.1 pins and registers for tmras (2/3) module specifications tmra45 tmra67 external clock input ta4in (shared with pl0) ta6in (shared with pl1) external pins timer flip-flop output ta5out (shared with pa4) ta7out (shared with pa5) timer run register ta45run (0x ffff_f113) ta67run (0xffff_f11b) timer control register ta45cr (0xffff_f112) ta67cr (0xffff_f11a) timer registers ta4reg (0xffff_f111) ta5reg (0xffff_f110) ta6reg (0xffff_f119) ta7reg (0xffff_f118) timer mode register ta45mod (0xffff_f117) ta67mod (0x ffff_f11f) timer flip-flop control register ta5ffcr (0xffff_f116) ta7ffcr (0xffff_f11e) timer interrupt mask register tag1im (0xffff_f115) registers (addresses) timer interrupt status register tag1st (0xffff_f114) table 11.1 pins and registers for tmras (3/3) module specifications tmra89 tmraab external clock input ta8in (shared with pl2) taain (shared with pl3) external pins timer flip-flop output ta9out (shared with pa6) tabout (shared with pa7) timer run register ta89run (0x ffff_f123) taabrun (0xffff_f12b) timer control register ta89cr (0xffff_f122) taabcr (0xffff_f12a) timer registers ta8reg (0xffff_f121) ta9reg (0xffff_f120) taareg (0xffff_f129) tabreg (0xffff_f128) timer mode register ta 89mod (0xffff_f127) t aabmod (0xffff_f12f) timer flip-flop control register ta9ffcr (0xffff_f126) tabffcr (0xffff_f12e) timer interrupt mask register tag2im (0xffff_f125) registers (addresses) timer interrupt status register tag2st (0xffff_f124) TMP1962C10BXBG 2006-02-21 tmp1962-205 11.1 tmra block diagram only the tmra01 block diagram is shown. the other timer modules are the same as the tmra01 except the pin and register names. run/clear prescaler cloc k source: t0 ta0trg external cloc k input: ta0in ta01mod TMP1962C10BXBG 2006-02-21 tmp1962-206 11.2 timer components 11.2.1 prescaler the tmra01 has a 9-bit prescaler that slows the rate of a cloc king source to the counters. the prescaler clock source ( t0) can be selected from fperiph/4, fperiph/8 and fperiph/16 by programming the prck[1:0] field of the syscr0 located within the cg. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the fpsel bit of the syscr1 located within the cg. the ta01prun bit in the ta01run register allows the enabling and disabling of the prescaler for the tmra01. a write of 1 to this bit starts the prescaler. a write of 0 to this bit clears and halts the prescaler. table 11.2 shows prescaler output clock resolutions. table 11.2 prescaler output clock resolutions @fc = 40.5 mhz prescaler output clock resolution peripheral clock source fpsel clock gear value gear[1:0] prescaler clock source prck[1:0] t1 t4 t16 t256 0(fgear) 00(fc) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 9 (12.6 s) fc/2 13 (202 s) 01(fperiph/8) fc/2 4 (0.4 s) fc/2 6 (1.58 s) fc/2 8 (6.32 s) fc/2 12 (101 s) 10(fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 11 (50.6 s) 01(fc/2) 00(fperiph/16) fc/2 6 (1.58 s) fc/2 8 (6.32 s) fc/2 10 (25.3 s) fc/2 14 (405 s) 01(fperiph/8) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 9 (12.6 s) fc/2 13 (202 s) 10(fperiph/4) fc/2 4 (0.4 s) fc/2 6 (1.58 s) fc/2 8 (6.32 s) fc/2 12 (101 s) 10(fc/4) 00(fperiph/16) fc/2 7 (3.16 s) fc/2 9 (12.6 s) fc/2 11 (50.6 s) fc/2 15 (809 s) 01(fperiph/8) fc/2 6 (1.58 s) fc/2 8 (6.32 s) fc/2 10 (25.3 s) fc/2 14 (405 s) 10(fperiph/4) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 9 (12.6 s) fc/2 13 (202 s) 11(fc/8) 00(fperiph/16) fc/2 8 (6.32 s) fc/2 10 (25.3 s) fc/2 12 (101 s) fc/2 16 (1618 s) 01(fperiph/8) fc/2 7 (3.16 s) fc/2 9 (12.6 s) fc/2 11 (50.6 s) fc/2 15 (809 s) 10(fperiph/4) fc/2 6 (1.58 s) fc/2 8 (6.32 s) fc/2 10 (25.3 s) fc/2 14 (405 s) 1(fc) 00(fc) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 9 (12.6 s) fc/2 13 (202 s) 01(fperiph/8) fc/2 4 (0.4 s) fc/2 6 (1.58 s) fc/2 8 (6.32 s) fc/2 12 (101 s) 10(fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 11 (50.6 s) 01(fc/2) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 9 (12.6 s) fc/2 13 (202 s) 01(fperiph/8) fc/2 4 (0.4 s) fc/2 6 (1.58 s) fc/2 8 (6.32 s) fc/2 12 (101 s) 10(fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 11 (50.6 s) 10(fc/4) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 9 (12.6 s) fc/2 13 (202 s) 01(fperiph/8) fc/2 4 (0.4 s) fc/2 6 (1.58 s) fc/2 8 (6.32 s) fc/2 12 (101 s) 10(fperiph/4) ? fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 11 (50.6 s) 11(fc/8) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 9 (12.6 s) fc/2 13 (202 s) 01(fperiph/8) ? fc/2 6 (1.58 s) fc/2 8 (6.32 s) fc/2 12 (101 s) 10(fperiph/4) ? fc/2 5 (0.79 s) fc/2 7 (3.16 s) fc/2 11 (50.6 s) note 1: the prescaler's output clock tn must be selected so that tn < fsys/2 is satisfied. note 2: do not change the clock gear value while the timer is running. note 3: the - character means "setting prohibited." TMP1962C10BXBG 2006-02-21 tmp1962-207 11.2.2 up-counters (uc0 and uc1) the timer module contains two 8-bit binary up-counters, each of which is driven by a clock independently selected by the ta01mod register. the clock input to the uc0 is eith er one of three prescaler outputs ( 1, t4, t16) or the external clock applied to the ta0in pin. which clock is to us e is programmed into the ta0clk[1:0] field of the ta01mod register. possible clock sources for the uc1 depend on the sel ected operating mode. if cascade connection is not used, the clock input to the uc1 is e ither one of three prescaler outputs ( 1, t16, t256) or the tmra0 comparator match-detect output. if cascade connection is used to select 16-bit timer mode, the clock input to the uc1 is the uc0 overflow output. if cascade connection is used for 24-bit timer mode, the uc1 overflow output is used as the clock input to the uc2 of the tmra23. if cascade connection is used for 32-bit timer mode, the uc2 overflow output is used as the clock input to the uc3. the ta0run and ta1run bits in the ta01run regist er are used to start counting and to stop and clear the counter. upon reset, the up-counter is set to 00h and the whole timer module is disabled. 11.2.3 timer registers (ta0reg and ta1reg) each timer register is an 8-bit register containing a time constant. when the up-counter reaches the time constant value in the timer register, the comparator block generates a match-detect signal. when the time constant is set to 00h, a match occurs upon a counter overflow. one of the two timer registers, ta0reg, is double-buffered. the double-buffering function can be enabled and disabled through the programming of the ta0rde bit in the ta01run: 0 = disable, 1 = enable. if double-buffering is enabled, the ta0reg latches a new time constant value from the register buffer. this takes place upon detection of a 2 n -1 overflow in pwm mode and upon a match between the uc0 and the ta1reg in ppg mode. double-buffering must be disabled in interval timer modes. a reset clears the ta01run.ta0rde bit to 0, disabling the double-buffering function. to use this function, the ta01run.ta0rde bit must be set to 1 after loading the ta0reg with a time constant. when ta01run.ta0rde = 1, the next time cons tant can be written to the register buffer. figure 11.2 illustrates the double-buffer structure for the ta0reg. TMP1962C10BXBG 2006-02-21 tmp1962-208 selector write shift trigger write to ta0reg 2 n -1 overflow in pwm mode ta01run TMP1962C10BXBG 2006-02-21 tmp1962-209 11.2.6 interrupt mask register (tag0im) tmra interrupts are classified into the following three groups: interrupt group 0 (inttag0): intta0, intta1, intta2, intta3 interrupt group 1 (inttag1): intta4, intta5, intta6, intta7 interrupt group 2 (inttag2): intta8, intta9, inttaa, inttab interrupts that belong to the same group are assumed as the same interrupt source when sent to the interrupt controller (intc). an inte rrupt mask register (t agnim) is provided fo r each interrupt group. setting a bit in the tagnim masks the corresponding in terrupt source so that the intc will not generate the interrupt. upon reset, all interr upt sources are enabled (not masked). 11.2.7 interrupt status register (tag0st) an interrupt status register (tagnst) is provided for each interrupt group. when an interrupt occurs, the flag bit corresponding to the interrupt source is set to 1. reading the tagnst register clears all bits that have been set. any interrupt sources masked in the tagnim register are disabled although flags are set when corresponding interrupts occur. note: if any of intta0 to intta3 occurs while the tag0st is being read, the corresponding flags are handled as follows: (if the flag is set and read simultaneously.) ? if 1 is read, the flag is cleared. ? if 0 is read, the flag is set after the read. TMP1962C10BXBG 2006-02-21 tmp1962-210 11.3 register description tmra01 run register 7 6 5 4 3 2 1 0 bit symbol ta0rde ta01c1 ta01c0 i2ta01 ta01prun ta1run ta0run read/write r/w r/w reset value 0 0 0 0 0 0 0 function double-bu ffering 0: disable 1: enable cascade connection 00: 8- or 16-bit mode 01: setting prohibited 10: setting prohibited 11: first stage of cascade idle 0: off 1: on timer run/stop control 0: stop & clear 1: run ta0run: runs or stops the tmra0. ta1run: runs or stops the tmra1. ta01prun: runs or stops the tmra01 prescaler. i2ta01: enables or disables the operat ion of the tmra0-tmra3 in idle mode. ta01c[1:0]: specifies how the tmra01 is used in cas cade connection. when this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the ta01m[1:0] bits in the tmra01 mode register. when this field is se t to 11 (first stage of cascade), the tmra01 is combined with the tmra23 to form a 24- or 32-bit timer. ta0rde: enables or disables double-buffering. tmra01 control register 7 6 5 4 3 2 1 0 bit symbol ta01en read/write r/w reset value 0 0 0 function tmra01 operation 0: disable 1: enable must be written as 00. ta01en: enables or disables the operation of the tmra01. if the tmra01 is disabled, no clock pulses are supplied to the tmra01 registers other than the ta01cr, so that power consumption in the system can be reduced (only the ta01cr can be read or written). to use the tmra01, set the ta01en bit to 1 before configuring other registers of the tmra01. once the tmra01 operates, all settings in its registers are held if it is disabled. the ta01en bit enables or disables the operation of the tmra0-tmra3. (enable or disable all channels of the tmra0-tmra3.) ta01run (0xffff_f103) note: bit 4 of the ta01run is read as undefined. ta01cr (0xffff_f102) note: bits 5 and 6 of the ta01cr are read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-211 tmra0 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmra1 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmra01 mode register 7 6 5 4 3 2 1 0 bit symbol ta01m1 ta01m0 pwm01 pwm00 ta1clk1 ta1clk0 ta0clk1 ta0clk0 read/write r/w reset value 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 - 1 10: 2 7 - 1 11: 2 8 - 1 tmra1 clock source 00: ta0trg 01: t1 (prescaler) 10: t16 (prescaler) 11: t256 (prescaler) tmra0 clock source 00: ta0in input 01: t1 (prescaler) 10: t4 (prescaler) 11: t16 (prescaler) ta0clk[1:0]: selects the tmra0 clock source. ta1clk[1:0]: selects the tmra1 clock source (when the ta01m[1:0] field is set to other than 01). when ta01m[1:0] = 01, the tmra0 overflow output is always the tmra1 clock source regardless of the settings in ta1clk[1:0]. pwm0[1:0]: selects the period for 8-bit pwm mode. the pwm period will be (2 n - 1) x clock source period. ta01m[1:0]: selects the tmra01 operating mode. when this field is set to 00, the tmra01 is used as two independent 8-bit timers, tmra0 and tmra1. ta0reg (0xffff_f101) note: bits 7-0 of the ta0reg are read as undefined. ta1reg (0xffff_f100) note: bits 7-0 of the ta1reg are read as undefined. ta01mod (0xffff_f107) TMP1962C10BXBG 2006-02-21 tmp1962-212 tmra1 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol taff1c1 taff1c0 taff1ie taff1is read/write r/w reset value 1 1 0 0 function 00: toggles ta1ff. (software toggle) 01: sets ta1ff to 1. 10: clears ta1ff to 0. 11: don't care. this field is always read as 11. ta1ff toggle enable 0: disable 1: enable ta1ff toggle trigger 0: tmra0 1: tmra1 taff1is: specifies whether timer flip-flop 1 (ta1ff) is toggled by a tmra0 match detection signal or a tmra1 match detection signal. this bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. tmrag0 interrupt mask register 7 6 5 4 3 2 1 0 bit symbol taim3 taim2 taim1 taim0 read/write r/w reset value 0 0 0 0 function 1: masks intta3. 1: masks intta2. 1: masks intta1. 1: masks intta0. tmrag0 status register 7 6 5 4 3 2 1 0 bit symbol intta3 intta2 intta1 intta0 read/write r reset value 0 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated ta1ffcr (0xffff_f106) note: bits 4, 5, 6 and 7 of the ta1ffcr are read as undefined. tag0im (0xffff_f105) note: bits 4, 5, 6 and 7 of the tag0im are read as undefined. tag0st (0xffff_f104) note 1: reading the tag0st register results in bits 0, 1, 2 and 3 being cleared. note 2: bits 4, 5, 6 and 7 of the tag0st are read as undefined. note 3: the flag bit corresponding to the interrupt source being masked is set, but the interrupt is not signaled. TMP1962C10BXBG 2006-02-21 tmp1962-213 tmra23 run register 7 6 5 4 3 2 1 0 bit symbol ta2rde ta23c1 ta23c0 i2ta23 ta23prun ta3run ta2run read/write r/w r/w reset value 0 0 0 0 0 0 0 function double-bu ffering 0: disable 1: enable cascade connection 00: 8- or 16-bit mode 01: 24-bit cascade 10: 32-bit cascade 11: setting prohibited idle 0: off 1: on timer run/stop control 0: stop & clear 1: run ta2run: runs or stops the tmra2. ta3run: runs or stops the tmra3. ta23prun: runs or stops the tmra23 prescaler. i2ta23: enables or disables the operat ion of the tmra0-tmra3 in idle mode. ta23c[1:0]: specifies how the tmra23 is used in cas cade connection. when this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the ta23m[1:0] bits in the tmra23 mode register. when this field is set to 01 (24-bit cascade), the tmra2 is cascaded with the tmra01. when this field is set to 10 (32-bit cascade), the tmra0 to tmra3 are cascaded. ta2rde: enables or disables double-buffering. tmra23 control register 7 6 5 4 3 2 1 0 bit symbol ta23en read/write r/w reset value 0 0 0 function tmra23 operation 0: disable 1: enable must be written as 00. ta23en: enables or disables the operation of the tmra23. if the tmra23 is disabled, no clock pulses are supplied to the tmra23 registers other than the ta23cr, so that power consumption in the system can be reduced (only the ta23cr can be read or written). to use the tmra23, set the ta23en bit to 1 before configuring other registers of the tmra23. once the tmra23 operates, all settings in its registers are held if it is disabled. ta23run (0xffff_f10b) note: bit 4 of the ta23run is read as undefined. ta23cr (0xffff_f10a) note: bits 5 and 6 of the ta23cr are read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-214 tmra2 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmra3 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmra23 mode register 7 6 5 4 3 2 1 0 bit symbol ta23m1 ta23m0 pwm21 pwm20 ta3clk1 ta3clk0 ta2clk1 ta2clk0 read/write r/w reset value 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 - 1 10: 2 7 - 1 11: 2 8 - 1 tmra3 clock source 00: ta2trg 01: t1 (prescaler) 10: t16 (prescaler) 11: t256 (prescaler) tmra2 clock source 00: ta2in input 01: t1 (prescaler) 10: t4 (prescaler) 11: t16 (prescaler) ta2clk[1:0]: selects the tmra2 clock source. ta3clk[1:0]: selects the tmra3 clock source (when the ta23m[1:0] field is set to other than 01). when ta23m[1:0] = 01, the tmra2 overflow output is always the tmra3 clock source regardless of the settings in ta3clk[1:0]. pwm2[1:0]: selects the period for 8-bit pwm mode. the pwm period will be (2 n - 1) x clock source period. ta23m[1:0]: selects the tmra23 operating mode. when this field is set to 00, the tmra23 is used as two independent 8-bit timers, tmra2 and tmra3. ta2reg (0xffff_f109) note: bits 7-0 of the ta2reg are read as undefined. ta3reg (0xffff_f108) note: bits 7-0 of the ta3reg are read as undefined. ta23mod (0xffff_f10f) TMP1962C10BXBG 2006-02-21 tmp1962-215 tmra3 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol taff3c1 taff3c0 taff3ie taff3is read/write r/w reset value 1 1 0 0 function 00: toggles ta3ff. (software toggle) 01: sets ta3ff to 1. 10: clears ta3ff to 0. 11: don't care. this field is always read as 11. ta3ff toggle enable 0: disable 1: enable ta3ff toggle trigger 0: tmra2 1: tmra3 taff3is: specifies whether timer flip-flop 3 (ta3ff) is toggled by a tmra2 match detection signal or a tmra3 match detection signal. this bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. tmra45 run register 7 6 5 4 3 2 1 0 bit symbol ta4rde ta45c1 ta45c0 i2ta45 ta45prun ta5run ta4run read/write r/w r/w reset value 0 0 0 0 0 0 0 function double-bu ffering 0: disable 1: enable cascade connection 00: 8- or 16-bit mode 01: setting prohibited 10: setting prohibited 11: first stage of cascade idle 0: off 1: on timer run/stop control 0: stop & clear 1: run ta4run: runs or stops the tmra4. ta5run: runs or stops the tmra5. ta45prun: runs or stops the tmra45 prescaler. i2ta45: enables or disables the operat ion of the tmra4-tmra7 in idle mode. ta45c[1:0]: specifies how the tmra45 is used in cas cade connection. when this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the ta45m[1:0] bits in the tmra45 mode register. when this field is se t to 11 (first stage of cascade), the tmra45 is combined with the tmra67 to form a 24- or 32-bit timer. ta4rde: enables or disables double-buffering. ta3ffcr (0xffff_f10e) note: bits 4, 5, 6 and 7 of the ta3ffcr are read as undefined. ta45run (0xffff_f113) note: bit 4 of the ta45run is read as undefined. TMP1962C10BXBG 2006-02-21 tmp1962-216 tmra45 control register 7 6 5 4 3 2 1 0 bit symbol ta45en read/write r/w reset value 0 0 0 function tmra45 operation 0: disable 1: enable must be written as 00. ta45en: enables or disables the operation of the tmra45. if the tmra45 is disabled, no clock pulses are supplied to the tmra45 registers other than the ta45cr, so that power consumption in the system can be reduced (only the ta45cr can be read or written). to use the tmra45, set the ta45en bit to 1 before configuring other registers of the tmra45. once the tmra45 operates, all settings in its registers are held if it is disabled. the ta45en bit enables or disables the operation of the tmra4-tmra7. (enable or disable all channels of the tmra4-tmra7.) tmra4 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmra5 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register ta45cr (0xffff_f112) note: bits 5 and 6 of the ta45cr are read as 0. ta4reg (0xffff_f111) note: bits 7-0 of the ta4reg are read as undefined. ta5reg (0xffff_f110) note: bits 7-0 of the ta5reg are read as undefined. TMP1962C10BXBG 2006-02-21 tmp1962-217 tmra45 mode register 7 6 5 4 3 2 1 0 bit symbol ta45m1 ta45m0 pwm41 pwm40 ta5clk1 ta5clk0 ta4clk1 ta4clk0 read/write r/w reset value 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 - 1 10: 2 7 - 1 11: 2 8 - 1 tmra5 clock source 00: ta4trg 01: t1 10: t16 11: t256 tmra4 clock source 00: ta4in input 01: t1 10: t4 11: t16 ta4clk[1:0]: selects the tmra4 clock source. ta5clk[1:0]: selects the tmra5 clock source (when the ta45m[1:0] field is set to other than 01). when ta45m[1:0] = 01, the tmra4 overflow output is always the tmra5 clock source regardless of the settings in ta5clk[1:0]. pwm4[1:0]: selects the period for 8-bit pwm mode. the pwm period will be (2 n - 1) x clock source period. ta45m[1:0]: selects the tmra45 operating mode. when this field is set to 00, the tmra45 is used as two independent 8-bit timers, tmra4 and tmra5. tmra5 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol taff5c1 taff5c0 taff5ie taff5is read/write r/w reset value 1 1 0 0 function 00: toggles ta5ff. (software toggle) 01: sets ta5ff to 1. 10: clears ta5ff to 0. 11: don't care. this field is always read as 11. ta5ff toggle enable 0: disable 1: enable ta5ff toggle trigger 0: tmra4 1: tmra5 taff5is: specifies whether timer flip-flop 5 (ta5ff) is toggled by a tmra4 match detection signal or a tmra5 match detection signal. this bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. tmrag1 interrupt mask register 7 6 5 4 3 2 1 0 bit symbol taim7 taim6 taim5 taim4 read/write r/w reset value 0 0 0 0 function 1: masks intta7. 1: masks intta6. 1: masks intta5. 1: masks intta4. ta45mod (0xffff_f117) ta5ffcr (0xffff_f116) note: bits 4, 5, 6 and 7 of the ta5ffcr are read as undefined. tag1im (0xffff_f115) note: bits 4, 5, 6 and 7 of the tag1im are read as undefined. TMP1962C10BXBG 2006-02-21 tmp1962-218 tmrag1 status register 7 6 5 4 3 2 1 0 bit symbol intta7 intta6 intta5 intta4 read/write r reset value 0 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated tmra67 run register 7 6 5 4 3 2 1 0 bit symbol ta6rde ta67c1 ta67c0 i2ta67 ta67prun ta7run ta6run read/write r/w r/w reset value 0 0 0 0 0 0 0 function double-bu ffering 0: disable 1: enable cascade connection 00: 8- or 16-bit mode 01: 24-bit cascade 10: 32-bit cascade 11: setting prohibited idle 0: off 1: on timer run/stop control 0: stop & clear 1: run ta6run: runs or stops the tmra6. ta7run: runs or stops the tmra7. ta67prun: runs or stops the tmra67 prescaler. i2ta67: enables or disables the operat ion of the tmra4-tmra7 in idle mode. ta67c[1:0]: specifies how the tmra67 is used in cas cade connection. when this field is set to 00, either 8- or 16-bit mode is selected accordi ng to the settings of the ta67m[1:0] bits in the tmra67 mode register. when this field is set to 01 (24-bit cascade), the tmra6 is cascaded with the tmra45. when this field is set to 10 (32-bit cascade), the tmra4 to tmra7 are cascaded. ta6rde: enables or disables double-buffering. tag1st (0xffff_f114) note 1: reading the tag1st register results in bits 0, 1, 2 and 3 being cleared. note 2: bits 4, 5, 6 and 7 of the tag1st are read as undefined. note 3: the flag bit corresponding to the interrupt source being masked is set, but the interrupt is not signaled. ta67run (0xffff_f11b) note: bit 4 of the ta67run is read as undefined. TMP1962C10BXBG 2006-02-21 tmp1962-219 tmra67 control register 7 6 5 4 3 2 1 0 bit symbol ta67en read/write r/w reset value 0 0 0 function tmra67 operation 0: disable 1: enable must be written as 00. ta67en: enables or disables the operation of the tmra67. if the tmra67 is disabled, no clock pulses are supplied to the tmra67 register s other than the ta67cr, so that power consumption in the system can be reduced (only the ta67cr can be read or written). to use the tmra67, set the ta67en bit to 1 before configuring other registers of the tmra67. once the tmra67 operates, all setti ngs in its registers are held if it is disabled. tmra6 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmra7 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register ta67cr (0xffff_f11a) note: bits 5 and 6 of the ta67cr are read as 0. ta6reg (0xffff_f119) note: bits 7-0 of the ta6reg are read as undefined. ta7reg (0xffff_f118) note: bits 7-0 of the ta7reg are read as undefined. TMP1962C10BXBG 2006-02-21 tmp1962-220 tmra67 mode register 7 6 5 4 3 2 1 0 bit symbol ta67m1 ta67m0 pwm61 pwm60 ta7clk1 ta7clk0 ta6clk1 ta6clk0 read/write r/w reset value 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 - 1 10: 2 7 - 1 11: 2 8 - 1 tmra7 clock source 00: ta6trg 01: t1 10: t16 11: t256 tmra6 clock source 00: ta6in input 01: t1 10: t4 11: t16 ta6clk[1:0]: selects the tmra6 clock source. ta7clk[1:0]: selects the tmra7 clock source (when the ta67m[1:0] field is set to other than 01). when ta67m[1:0] = 01, the tmra6 overflow output is always the tmra7 clock source regardless of the settings in ta7clk[1:0]. pwm6[1:0]: selects the period for 8-bit pwm mode. the pwm period will be (2 n - 1) x clock source period. ta67m[1:0]: selects the tmra67 operating mode. when this field is set to 00, the tmra67 is used as two independent 8-bit timers, tmra6 and tmra7. tmra7 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol taff7c1 taff7c0 taff7ie taff7is read/write r/w reset value 1 1 0 0 function 00: toggles ta7ff. (software toggle) 01: sets ta7ff to 1. 10: clears ta7ff to 0. 11: don't care. this field is always read as 11. ta7ff toggle enable 0: disable 1: enable ta7ff toggle trigger 0: tmra6 1: tmra7 taff7is: specifies whether timer flip-flop 7 (ta7ff) is toggled by a tmra6 match detection signal or a tmra7 match detection signal. this bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. ta67mod (0xffff_f11f) ta7ffcr (0xffff_f11e) note: bits 4, 5, 6 and 7 of the ta7ffcr are read as undefined. TMP1962C10BXBG 2006-02-21 tmp1962-221 tmra89 run register 7 6 5 4 3 2 1 0 bit symbol ta8rde ta89c1 ta89c0 i2ta89 ta89prun ta9run ta8run read/write r/w r/w reset value 0 0 0 0 0 0 0 function double-bu ffering 0: disable 1: enable cascade connection 00: 8- or 16-bit mode 01: setting prohibited 10: setting prohibited 11: first stage of cascade idle 0: off 1: on timer run/stop control 0: stop & clear 1: run ta8run: runs or stops the tmra8. ta9run: runs or stops the tmra9. ta89prun: runs or stops the tmra89 prescaler. i2ta89: enables or disables the operat ion of the tmra8-tmrab in idle mode. ta89c[1:0]: specifies how the tmra89 is used in cas cade connection. when this field is set to 00, either 8- or 16-bit mode is selected accordi ng to the settings of the ta89m[1:0] bits in the tmra89 mode register. when this field is set to 11 (first stage of cascade), the tmra89 is combined with the tmraab to form a 24- or 32-bit timer. ta8rde: enables or disables double-buffering. tmra89 control register 7 6 5 4 3 2 1 0 bit symbol ta89en read/write r/w reset value 0 0 0 function tmra89 operation 0: disable 1: enable must be written as 00. ta89en: enables or disables the operation of the tmra89. if the tmra89 is disabled, no clock pulses are supplied to the tmra89 registers other than the ta89cr, so that power consumption in the system can be reduced (only the ta89cr can be read or written). to use the tmra89, set the ta89en bit to 1 before configuring other registers of the tmra89. once the tmra89 oper ates, all settings in its registers are held if it is disabled. the ta89en bit enables or di sables the operation of the tmra8-tmrab. (enable or disable all channels of the tmra8-tmrab.) ta89run (0xffff_f123) note: bit 4 of the ta89run is read as undefined. ta89cr (0xffff_f122) note: bits 5 and 6 of the ta89cr are read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-222 tmra8 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmra9 register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmra89 mode register 7 6 5 4 3 2 1 0 bit symbol ta89m1 ta89m0 pwm81 pwm80 ta9clk1 ta9clk0 ta8clk1 ta8clk0 read/write r/w reset value 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 - 1 10: 2 7 - 1 11: 2 8 - 1 tmra9 clock source 00: ta8trg 01: t1 10: t16 11: t256 tmra8 clock source 00: ta8in input 01: t1 10: t4 11: t16 ta8clk[1:0]: selects the tmra8 clock source. ta9clk[1:0]: selects the tmra9 clock source (when the ta89m[1:0] field is set to other than 01). when ta89m[1:0] = 01, the tmra8 overflow output is always the tmra9 clock source regardless of the settings in ta9clk[1:0]. pwm8[1:0]: selects the period for 8-bit pwm mode. the pwm period will be (2 n - 1) x clock source period. ta89m[1:0]: selects the tmra89 operating mode. when this field is set to 00, the tmra89 is used as two independent 8-bit timers, tmra8 and tmra9. ta8reg (0xffff_f121) note: bits 7-0 of the ta8reg are read as undefined. ta9reg (0xffff_f120) note: note: bits 7-0 of the ta9reg are read as undefined. ta89mod (0xffff_f127) TMP1962C10BXBG 2006-02-21 tmp1962-223 tmra9 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol taff9c1 taff9c0 taff9ie taff9is read/write r/w reset value 1 1 0 0 function 00: toggles ta9ff. (software toggle) 01: sets ta9ff to 1. 10: clears ta9ff to 0. 11: don't care. this field is always read as 11. ta9ff toggle enable 0: disable 1: enable ta9ff toggle trigger 0: tmra8 1: tmra9 taff9is: specifies whether timer flip-flop 9 (ta9ff) is toggled by a tmra8 match detection signal or a tmra9 match detection signal. this bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. tmrag2 interrupt mask register 7 6 5 4 3 2 1 0 bit symbol taimb taima taim9 taim8 read/write r/w reset value 0 0 0 0 function 1: masks inttab. 1: masks inttaa. 1: masks intta9. 1: masks intta8. tmrag2 status register 7 6 5 4 3 2 1 0 bit symbol inttab inttaa intta9 intta8 read/write r reset value 0 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated ta9ffcr (0xffff_f126) note: bits 4, 5, 6 and 7 of the ta9ffcr are read as undefined. tag2im (0xffff_f125) note: bits 4, 5, 6 and 7 of the tag2im are read as undefined. tag2st (0xffff_f124) note 1: reading the tag2st register results in bits 0, 1, 2 and 3 being cleared. note 2: bits 4, 5, 6 and 7 of the tag2st are read as undefined. note 3: the flag bit corresponding to the interrupt source being masked is set, but the interrupt is not signaled. TMP1962C10BXBG 2006-02-21 tmp1962-224 tmraab run register 7 6 5 4 3 2 1 0 bit symbol taarde taabc1 taabc0 i2taab taabprun tabrun taarun read/write r/w r/w reset value 0 0 0 0 0 0 0 function double-bu ffering 0: disable 1: enable cascade connection 00: 8- or 16-bit mode 01: 24-bit cascade 10: 32-bit cascade 11: setting prohibited idle 0: off 1: on timer run/stop control 0: stop & clear 1: run taarun: runs or stops the tmraa. tabrun: runs or stops the tmrab. taabprun: runs or stops the tmraab prescaler. i2taab: enables or disables the operat ion of the tmra8-tmrab in idle mode. taabc[1:0]: specifies how the tmraab is used in cascade connection. when this field is set to 00, either 8- or 16-bit mode is selected according to the settings of the taabm[1:0] bits in the tmraab mode register. when this field is set to 01 (24-bit cascade), the tmraa is cascaded with the tmra89. when this field is set to 10 (32-bit cascade), the tmra8 to tmrab are cascaded. taarde: enables or disables double-buffering. tmraab control register 7 6 5 4 3 2 1 0 bit symbol taaben read/write r/w reset value 0 0 0 function tmraab operation 0: disable 1: enable must be written as 00. taaben: enables or disables the operation of the tmraab. if the tmraab is disabled, no clock pulses are supplied to the tmraab registers other than the taabcr, so that power consumption in the system can be reduced (only the taabcr can be read or written). to use the tmraab, set the taaben bit to 1 before configuring other registers of the tmraab. once the tmraab operates, all settings in its registers are held if it is disabled. taabrun (0xffff_f12b) note: bit 4 of the taabrun is read as undefined. taabcr (0xffff_f12a) note: bits 5 and 6 of the taabcr are read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-225 tmraa register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmrab register 7 6 5 4 3 2 1 0 bit symbol read/write w function timer register tmraab mode register 7 6 5 4 3 2 1 0 bit symbol taabm1 taabm0 pwma1 pwma0 tabclk1 tabclk0 taaclk1 taaclk0 read/write r/w reset value 0 0 0 0 0 0 0 0 function operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 - 1 10: 2 7 - 1 11: 2 8 - 1 tmrab clock source 00: taatrg 01: t1 10: t16 11: t256 tmraa clock source 00: taain input 01: t1 10: t4 11: t16 taaclk[1:0]: selects the tmraa clock source. tabclk[1:0]: selects the tmrab clock source (when the taabm[1:0] field is set to other than 01). when taabm[1:0] = 01, the tmraa overflow output is always the tmrab clock source regardless of the settings in tabclk[1:0]. pwma[1:0]: selects the period for 8-bit pwm mode. the pwm period will be (2 n - 1) x clock source period. taabm[1:0]: selects the tmraab operating mode. when this field is set to 00, the tmraab is used as two independent 8-bit timers, tmraa and tmrab. taareg (0xffff_f129) note: bits 7-0 of the taareg are read as undefined. tabreg (0xffff_f128) note: bits 7-0 of the tabreg are read as undefined. taabmod (0xffff_f12f) TMP1962C10BXBG 2006-02-21 tmp1962-226 tmrab flip-flop control register 7 6 5 4 3 2 1 0 bit symbol taffbc1 taffbc0 taffbie taffbis read/write r/w reset value 1 1 0 0 function 00: toggles tabff. (software toggle) 01: sets tabff to 1. 10: clears tabff to 0. 11: don't care. this field is always read as 11. tabff toggle enable 0: disable 1: enable ta3ff toggle trigger 0: tmraa 1: tmrab taffbis: specifies whether timer flip-flop b (tabff) is toggled by a tmraa match detection signal or a tmrab match detection signal. this bit is valid only in 8-bit timer mode; it is a don't-care bit in other modes. tabffcr (0xffff_f12e) note: bits 4, 5, 6 and 7 of the tabffcr are read as undefined. TMP1962C10BXBG 2006-02-21 tmp1962-227 11.4 operating modes 11.4.1 8-bit interval timer mode the tmra0 and the tmra1 can be independently programmed as 8-bit interval timers. programming these timers should only be attempted when the timers are not running. (1) generating periodic interrupts in the following example, the tmra 1 is used to accomplish periodic interrupt generation. first, stop the tmra1 (if it is running). then, set the operating mode, clock source and interrupt interval in the ta01mod and ta1reg registers. then, enable the intta1 interrupt and start the tmra1. example: generating the intta1 interrupt at a 20-s interval (fc = 40.5 mhz) clocking conditions: system clock: high-speed (fc) prescaler clock: fperiph/4 (fperiph = fsys) msb lsb 7 6 5 4 3210 ta01run ? 0 0 x ? ? 0 ? stops and clears the tmra1. ta01mod 0 0 x x 1 0 x x selects 8-bit interval timer mode and t1 as the clock source (which provides a 0.2-s resolution @fc = 40.5 mhz). ta1reg 0 1 1 0 0100 sets the time constant value in the ta1reg (20 s t1 = 100 (64h)). imc6lh x x 1 1 0101 e nables inttaga0 and sets the interrupt level to 5. intta1 must always be programmed to be rising-edge triggered. ta01run ? ? ? x ? 11? starts the tmra1. x = don't care, - = no change refer to table 11.2 when selecting a timer clock source. note: the clock inputs to the tmra0 and the tmra1 can be one of the following: tmra0: ta0in input, t1, t4 or t16 tmra1: match-detect signal from the tmra0, t1, t16 or t256 TMP1962C10BXBG 2006-02-21 tmp1962-228 (2) generating a square wave with a 50% duty cycle the 8-bit interval timer mode can be used to generate square-wave output. this is accomplished by toggling the timer flip-flop (ta1ff) periodically. the ta1ff state can be driven out to the ta1out pin. both the tmra0 and the tmra1 can be used as square-wave generators. the following shows an example using the tmra1. example: generating square-wave output wi th a 1.2-s period on the ta1out pin (fc = 40.5 mhz) clocking conditions: system clock: high-speed (fc) high-speed clock gear: x1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) 7 6 5 4 3210 ta01run ? 0 0 x ? ? 0 ? stops and clears the tmra1. ta01mod 0 0 x x 0 1 ? ? selects 8-bit interval timer mode and t1 as the clock source (which provides a 0.2-s resolution @fc = 40.5 mhz). ta1reg 0 0 0 0 0011 sets the time constant value in the ta1reg (1.2 s t1 2 = 3). ta1ffcr x x x x 1011 clears the ta1ff to 0 and selects the tmra1 match-detect output as a toggle-trigger signal. pacr ? ? ? ? ? ? 1 ? pafc ? ? ? ? ? ? 1 ? configures pa1 as the ta1out output pin. ta01run ? ? ? x ? 11? starts the tmra1. x = don't care, ? = no change 0.6 s @fc = 40.5 mhz bit7 - 2 t1 intta1 up-counter clea r ta1ff bit0 bit1 ta01run TMP1962C10BXBG 2006-02-21 tmp1962-229 (3) using the tmra0 match-detect output as a trigger for the tmra1 set the tmra01 in 8-bit interval timer mode. se lect the tmra0 comparator match-detect output as the clock source for the tmra1. 3451 1 22 33 45 2 tmra1 up-counter (when ta1reg = 2) tmra0 up-counter (when ta0reg = 5) 1 12 1 tmra0 comparator match output tmra1 match output figure 11.4 using the tmra0 match-dete ct output as a trigger for the tmra1 11.4.2 16/24/32-bit interval timer mode (1) 16-bit interval timer mode the tmra0 and the tmra1 are cascadable to form a 16-bit interval timer. the tmra01 is put in 16-bit interval timer mode by programming the ta01m[1:0] field in the ta01mod register to 01. in 16-bit interval timer mode, the tmra1 is clocked by the counter overflow output from the tmra0. in this mode, the ta1clk[1:0] bits in the ta01mod register are don't-cares. the clock input to the tmra0 can be sel ected as shown in table 11.4. write the lower eight bits of a time constant value to the ta0reg and the upper eight bits to the ta1reg. programming these registers should only be attempted when the timers are not running. example: generating the intta1 interrupt at a 0.1-second interval (fc = 40.5 mhz) clocking conditions: system clock: high-speed (fc) high-speed clock gear: x1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) under the above conditions, t16 has a period of 3.16 s @ 40.5 mhz. when t16 is used as the tmra0 clock source, the required time constant value is calculated as follows: 0.1 s 3.16 s = 31646 = 7b9eh thus, the ta1reg is to be set to 7bh and the ta0reg to 9eh. TMP1962C10BXBG 2006-02-21 tmp1962-230 every time the up-counter uc0 reaches the value in the ta0reg, the tmra0 comparator generates a match-detect output, but the uc0 continues counting up. a match between the uc0 and the ta0reg does not cause an intta0 interrupt. every time the up-counter uc1 reaches the value in the ta1reg, the tmra1 comparator generates a match-detect output. when the tmra0 and tmra1 match-detect outputs are asserted simultaneously, both the up-counters (uc0 and uc1) are reset to 00h and an interrupt is generated on intta1. also, if so enabled, the timer flip-flop (ta1ff) is toggled. example: ta1reg = 04h and ta0reg = 80h 0080h 0180h 0280h 0380h 0480h up-counter values (uc1/uc0) toggled match-detect signal from the tmra0 comparator intta1 interrupt 0000h ta1out timer output figure 11.5 timer output in 16-bit interval timer mode (2) 24-bit interval timer mode the pair of the tmra0 and tmra1 can further be cascaded with the tmra2 to form a 24-bit interval timer. in 24-bit interval timer mode, the tmra1 is clocked by the counter overflow output from the tmra0. in this mode, the ta1clk[1:0] bits in the ta01mod register are don't-cares. the tmra2 is clocked by the counter overflow output from the tmra1. the clock input to the tmra0 can be selected as shown in table 11.4. write the lowest eight bits of a time constant value to the ta0reg, the middle eight bits to the ta1reg and the highest eight bits to the ta2reg. programming these registers should only be attempted when the timers are not running. (3) 32-bit interval timer mode the tmra0, tmra1, tmra2 and tmra3 are put in 32-bit interval timer mode by programming the ta01m[1:0] field in the ta01mod register to 01 and the ta32m0 bit in the ta32mod register to 1. in 32-bit interval timer mode, the tmra1 is clocked by the counter overflow output from the tmra0. in this mode, the ta1clk[1:0] bits in the ta01mod register are don't-cares. likewise, the tmra3 is clocked by the counter overflow output from the tmra2 and the ta3clk[1:0] bits in the ta23mod register are don' t-cares. the tmra2 is clocked by the counter overflow output from the tmra1. the clock input to the tmra 0 can be selected as shown in table 11.4. write the lowest eight bits of a time constant value to the ta0reg, the next eight bits to the ta1reg, the next eight bits to the ta2reg and the highest eight bits to the ta3reg. programming these registers should only be attempted when the timers are not running. TMP1962C10BXBG 2006-02-21 tmp1962-231 (4) cascade combinations in 16-bit interval timer mode: upper lower upper lower tmra3 tmra2 tmra1 tmra0 tmra7 tmra6 tmra5 tmra4 tmrab tmraa tmra9 tmra8 in 24-bit interval timer mode: highest lowest tmra2 tmra1 tmra0 tmra6 tmra5 tmra4 tmraa tmra9 tmra8 in 32-bit interval timer mode: highest lowest tmra3 tmra2 tmra1 tmra0 tmra7 tmra6 tmra5 tmra4 tmrab tmraa tmra9 tmra8 11.4.3 8-bit programmable pulse generation (ppg) mode the 8-bit ppg mode can be used to generate a square wave with any frequency and duty cycle, as shown below. the pulse can be high-going and low-going, as determined by the initial setting of the timer flip-flop (ta1ff). this mode is supported by the tmra0, but not by the tmra1. the square wave output is driven to the ta1out pin (which is multiplexed with pa1). t match between ta0reg and up-counter 0 (intta0) t h t l ta0reg ta1reg match between ta1reg and up-counter 0 (intta1) ta1out figure 11.6 8-bit ppg output waveform note: in 24-bit interval timer mode, the tmra3, tmra7 and tmrab can operate as an independent 8-bit timer. TMP1962C10BXBG 2006-02-21 tmp1962-232 in this mode, a square wave is generated by togg ling the timer flip-flop (ta1ff). the ta1ff changes state every time a match is detected between th e uc0 and the ta0reg and between the uc0 and the ta1reg. the ta0reg must be set to a value less than the ta1reg value. in this mode, the tmra1 up-counter (uc1) cannot be independently used; however, the tmra1 must be put in a running state by setting the ta1run bit in the ta01run register to 1. figure 11.7 shows a functional diagram of 8-bit ppg mode. shift-trigger selector t1 t4 t16 ta01run TMP1962C10BXBG 2006-02-21 tmp1962-233 example: generating a 50-khz square wave with a 25% duty cycle (fc = 40.5 mhz) 20 s clocking conditions: system clock: high-speed (fc) high-speed clock gear: x1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) the time constant values to be loaded into the ta0reg and ta1reg are determined as follows: a 50-khz waveform has a period of 20 s. under the above clocking conditions, t1 has a 0.2-s resolution (@fc = 40.5 mhz). when t1 is used as the timer clock source, the ta1reg should be loaded with: 20 s 0.2 s = 100 (64h) with a 25% duty cycle, the high pulse width is calculated as 20 s 1/4 = 5 s. thus, the ta0reg should be loaded with: 5 s 0.2 s = 25 (19h) 7 6 5 4 3210 ta01run 0 0 0 x ? 0 0 0 stops and clears the tmra0 and the tmra1. ta01mod 1 0 x x x x 0 1 selects 8-bit ppg mode and t1 as the clock source. ta0reg 0 0 0 1 1001 writes 19h. ta1reg 0 1 1 0 0100 writes 64h. ta1ffcr x x x x 011x sets the ta1ff to 1 and enables toggling. if these bits are set to 10, a low-going pulse is generated. pacr ? ? ? ? ? ? 1 ? pafc ? ? ? ? ? ? 1 ? configures pa1 as the ta1out output pin. ta01run 1 ? ? x ? 1 1 1 starts the tmra0 and the tmra1. x = don't care, ? = no change TMP1962C10BXBG 2006-02-21 tmp1962-234 11.4.4 8-bit pwm generation mode the tmra0 can be used as a pulse-width modulated (pwm) signal generator with up to 8 bits of resolution. this mode is supported by the tmra0, but not by the tmra1. the pwm signal is driven out on the ta1out pin (which is multiplexed with p71). while the tmra01 is in this mode, the tmra1 is usable as an 8-bit interval timer. the timer flip-flop toggles when the up-counter (uc0) reaches the ta0reg value and when a 2 n -1 counter overflow occurs, where n is programmable to 6, 7 or 8 through the pwm[01:00] field in the ta01mod register. the uc0 is reset to 00h upon a 2 n -1 overflow. in 8-bit pwm generation mode, the following must be satisfied: (ta0reg value) < (2 n -1 counter overflow value) (ta0reg value) 0 ta1out 2 n -1 overflo w (intta0 interrupt) t pwm (pwm cycle) match between ta0reg and up-counter 0 figure 11.9 8-bit pwm signal generation figure 11.10 shows a functional diagram of 8-bit pwm generation mode. ta01mod TMP1962C10BXBG 2006-02-21 tmp1962-235 in 8-bit pwm generation mode, if the double-buffering function is enabled, the ta0reg value (i.e., the duty cycle) can be changed dynamically by writi ng a new value into the register buffer. upon a 2 n -1 counter overflow, the ta0reg latches a new value from the register buffer. the ta0reg can be loaded with a new value upon every counter overflow, thus making it easy to generate a pwm signal with a variable duty cycle. q 2 up-counter = q 2 up-counter = q 1 q 1 q 2 q 3 shift into ta0reg match between ta0reg and up-counter 0 2 n -1 overflo w ta0reg (compare value) register buffe r write to ta0reg (register buffer) figure 11.11 register buffer operation example: generating a pwm signal as show n below on the ta1out pin (fc = 40.5 mhz) 20 s 25 s clocking conditions: system clock: high-speed (fc) high-speed clock gear: x1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) under the above conditions, t1 has a 0.2-s (0.197-s) period (@fc = 40.5 mhz). 25 s 0.197 s = 127 which is equal to 2 7 - 1. 20 s 0.2 s = 100 = 64h hence, the time constant value to be programmed into the ta0reg is 64h. msb lsb 7 6 5 4 3210 ta01run ? 0 0 x ? ? ? 0 stops and clears the tmra0. ta01mod 1 1 1 0 ? ? 0 1 selects 8-bit pwm mode (period = 2 7 -1) and t1 as the clock source. ta0reg 0 1 1 0 0100 writes 64h. ta1ffcr x x x x 101x clears the ta1ff to 0 and enables toggling. pacr ? ? ? ? ? ? 1 ? pafc ? ? ? ? ? ? 1 ? configures pa1 as the ta1out output pin. ta01run 1 ? ? x ? 1 ? 1 starts the tmra0. x = don't care, ? = no change TMP1962C10BXBG 2006-02-21 tmp1962-236 table 11.3 pwm period @fc = 40.5 mhz pwm period 2 6 -1 2 7 -1 2 8 -1 peripheral clock select fpsel clock gear value gear[1:0] prescaler clock source prck[1:0] t1 t4 t16 t1 t4 t16 t1 t4 t16 0(fgear) 00(fc) 00(fperiph/16) 49.8 s 199 s 796 s 100 s 401 s 1.61 ms 201 s 806 s 3.22 ms 01(fperiph/8) 24.9 s 99.6 s 398 s 50.2 s 201 s 803 s 101 s 403 s 1.61 ms 10(fperiph/4) 12.4 s 49.8 s 199 s 25.1 s 100 s 401 s 50.3 s 201 s 806 s 01(fc/2) 00(fperiph/16) 99.6 s 398 s 1.59 ms 201 s 803 s 3.21 ms 403 s 1.61 ms 6.45 ms 01(fperiph/8) 49.8 s 199 s 796 s 100 s 401 s 1.61 ms 201 s 806 s 3.22 ms 10(fperiph/4) 24.9 s 99.6 s 398 s 50.2 s 201 s 803 s 101 s 403 s 1.61 ms 10(fc/4) 00(fperiph/16) 199 s 796 s 3.19 ms 401 s 1.61 ms 6.42 ms 806 s 3.22 ms 12.9 ms 01(fperiph/8) 99.6 s 398 s 1.59 ms 201 s 803 s 3.21 ms 403 s 1.61 ms 6.45 ms 10(fperiph/4) 49.8 s 199 s 796 s 100 s 401 s 1.61 ms 201 s 806 s 3.22 ms 11(fc/8) 00(fperiph/16) 398 s 1.59 ms 6.37 ms 803 s 3.21 ms 12.8 ms 1.61 ms 6.45 ms 25.8 ms 01(fperiph/8) 199 s 796 s 3.19 ms 401 s 1.61 ms 6.42 ms 806 s 3.22 ms 12.9 ms 10(fperiph/4) 99.6 s 398 s 1.59 ms 201 s 803 s 3.21 ms 403 s 1.61 ms 6.45 ms 1(fc) 00(fc) 00(fperiph/16) 49.8 s 199 s 796 s 100 s 401 s 1.61 ms 201 s 806 s 3.22 ms 01(fperiph/8) 24.9 s 99.6 s 398 s 50.2 s 201 s 803 s 101 s 403 s 1.61 ms 10(fperiph/4) 12.4 s 49.8 s 199 s 25.1 s 100 s 401 s 50.3 s 201 s 806 s 01(fc/2) 00(fperiph/16) 49.8 s 199 s 796 s 100 s 401 s 1.61 ms 201 s 806 s 3.22 ms 01(fperiph/8) 24.9 s 99.6 s 398 s 50.2 s 201 s 803 s 101 s 403 s 1.61 ms 10(fperiph/4) 12.4 s 49.8 s 199 s 25.1 s 100 s 401 s 50.3 s 201 s 806 s 10(fc/4) 00(fperiph/16) 49.8 s 199 s 796 s 100 s 401 s 1.61 ms 201 s 806 s 3.22 ms 01(fperiph/8) 24.9 s 99.6 s 398 s 50.2 s 201 s 803 s 101 s 403 s 1.61 ms 10(fperiph/4) ? 49.8 s 199 s ? 100 s 401 s ? 201 s 806 s 11(fc/8) 00(fperiph/16) 49.8 s 199 s 796 s 100 s 401 s 1.61 ms 201 s 806 s 3.22 ms 01(fperiph/8) ? 99.6 s 398 s ? 201 s 803 s ? 403 s 1.61 ms 10(fperiph/4) ? 49.8 s 199 s ? 100 s 401 s ? 201 s 806 s note 1: the prescaler's output clock tn must be selected so that tn < fsys/2 is satisfied. note 2: the - character means "setting prohibited." TMP1962C10BXBG 2006-02-21 tmp1962-237 11.4.5 operating mode summary table 11.4 shows the settings for the tmra01 for each of the operating modes. table 11.4 register settings for each operating mode register ta01run ta01mod ta1ffcr field TMP1962C10BXBG 2006-02-21 tmp1962-238 12. 16-bit timer/event counters (tmrbs) the tmp1962 has a 16-bit timer/event counter consisting of four identical channels (tmrb0-tmrb3). each channel has the following four basic operating modes: ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit programmable pulse generation (ppg) mode ? 2-phase pulse input counter mode (tmrb2 and tmrb3 only) each channel has the capture capability used to latch the value of the counter. the capture capability allows: ? frequency measurement ? pulse width measurement ? time difference measurement the main components of a tmrbn block are a 16-bit up-counter, two 16-bit timer registers (one of which is double-buffered), two 16-bit capture registers, two compar ators, capture control logic, a timer flip-flop and its associated control logic. a total of thirteen registers provid e control over the operating modes an d timer flip-flops for each of the tmrb0 to tmrb3. each channel is independently programmable and functionally equivalent except that the tmrb2 and tmrb3 support the 2-phase pulse count function. in the following sections, any references to the tmrb0 also apply to all the other channels. table 12.1 gives the pins and registers for the four channels. table 12.1 pins and registers for the tmrb0-tmrb3 channel specifications tmrb0 tmrb1 tmrb2 tmrb3 external clock/capture trigger inputs tb0in0 (shared with pl4) tb0in1 (shared with pl5) tb1in0 (shared with pl6) tb1in1 (shared with pl7) tb2in0 (shared with pb2) tb2in1 (shared with pb3) tb3in0 (shared with pb5) tb3in1 (shared with pb6) capture trigger timer ta3out ta3out ta3out ta3out external pins timer flip-flop output tb0out (shared wi th pb0) tb1out (shared with pb1) tb2out (shared with pb4) tb3out (shared with pb7) timer run register tb0run (0xffff_f143) tb1run (0 xffff_f153) tb2run (0xffff_f163) tb3run (0xffff_f173) timer control register tb0cr (0xffff_f142) tb1cr (0 xffff_f152) tb2cr (0xffff_f162) tb3cr (0xffff_f172) timer mode register tb0mod (0xff ff_f141) tb1mod (0xffff_f151) tb2mod (0xffff_f161) tb3mod (0xffff_f171) timer flip-flop control register tb0ffcr (0xffff_f140) tb1ffcr (0xffff_f150) tb2ffcr(0xffff_f160) tb3ffcr (0xffff_f170) timer status register tb0st (0xffff_f147) tb1st (0 xffff_f157) tb2st (0xffff_f167) tb3st (0xffff_f177) timer registers tb0rg0l (0xffff_f14b) tb0rg0h (0xffff_f14a) tb0rg1l (0xffff_f149) tb0rg1h (0xffff_f148) tb1rg0l (0xffff_f15b) tb1rg0h (0xffff_f15a) tb1rg1l (0xffff_f159) tb1rg1h (0xffff_f158) tb2rg0l (0xffff_f16b) tb2rg0h (0xffff_f16a) tb2rg1l (0xffff_f169) tb2rg1h (0xffff_f168) tb3rg0l (0xffff_f17b) tb3rg0h (0xffff_f17a) tb3rg1l (0xffff_f179) tb3rg1h (0xffff_f178) registers (addresses) capture registers tb0cp0l (0xffff_f14f) tb0cp0h (0xffff_f14e) tb0cp1l (0xffff_f14d) tb0cp1h (0xffff_f14c) tb1cp0l (0xffff_f15f) tb1cp0h (0xffff_f15e) tb1cp1l (0xffff_f15d) tb1cp1h (0xffff_f15c) tb2cp0l (0xffff_f16f) tb2cp0h (0xffff_f16e) tb2cp1l (0xffff_f16d) tb2cp1h (0xffff_f16c) tb3cp0l (0xffff_f17f) tb3cp0h (0xffff_f17e) tb3cp1l (0xffff_f17d) tb3cp1h (0xffff_f17c) TMP1962C10BXBG 2006-02-21 tmp1962-239 12.1 block diagrams internal data bus internal data bus run/ clear match detect 16-bit comparator (cp0) 16-bit timer register tb0rg0h/l 16-bit comparator (cp1) register buffer 0 16-bit timer register tb0rg1h/l match detect counter clock tb0mod TMP1962C10BXBG 2006-02-21 tmp1962-240 internal data bus internal data bus run/ clear match detect 16-bit comparator (cp0) 16-bit timer register tb2rg0h/l 16-bit comparator (cp1) register buffer 0 16-bit timer register tb2rg1h/l match detect counter clock tb2mod TMP1962C10BXBG 2006-02-21 tmp1962-242 12.2.2 up-counter (uc0) the tmrb0 contains a 16-bit binary up-counter, which is driven by a clock selected by the tb0clk[1:0] field in the tb0mod register. the clock input to the uc0 is eith er one of three prescaler outputs ( 1, t4, t16) or the external clock applied to the tb0in0 pin. the tb0run bit in the tb0run register is used to start the uc0 and to stop and clear the uc0. the uc0 is cleared to 0000h , if so enabled, when it reaches the value in the tb0rg1h/l register. the tb0cle bit in the tb0mod register allows the user to enable and disable this clearing. if it is disabled, the uc0 acts as a free-running counter. an overflow interrupt (inttb01) is generated upon a counter overflow. the tmrb2 and tmrb3 support the 2-phase pulse input count function. setting the tb2udce bit in the tr2run register to 1 selects 2-phase pulse count mode, causing the tm rb2 to operate as an up/down counter, which is initialized to 0x7fff. when the counter overflows, it is reloaded with 0x0000. when the counter underflows, it is reloaded with 0xffff. in other modes, the tmrb2 and tmrb3 only operate as up-counters. 12.2.3 timer registers (tb0rg0h/l and tb0rg1h/l) each timer channel has two 16-bit timer registers containing a time constant. when the up-counter reaches the time constant value in each timer regist er, the associated comparator block generates a match-detect signal. each of the timer registers (tb0rg0h/l, tb0rg1h/ l) can be written with either a halfword-store instruction or a series of two byte-store instructions. when byte-store instructions are used, the low-order byte must be stored first, followed by the high-order byte. one of the two timer registers, tb0rg0, is double-buffered. the double-buffering function can be enabled and disabled through the programming of the tb0rde bit in the tb0run: 0=disable, 1=enable. if double-buffering is enabled, the tb0rg0 latches a new time constant value from the register buffer. this takes place when a match is detected between the uc0 and the tb0rg1. upon reset, the contents of the tb0rg0 and tb0rg1 are undefined; thus, they must be loaded with valid values before the timer can be used. a reset clears the tb0run.tb0rde bit to 0, disabling the double-buffering function. to use this function, th e tb0run.tb0rde bit must be set to 1 after loading the tb0rg0 and tb0rg1 with time constants. when tb0run.tb0rde=1, the next time constant can be written to the register buffer. the tb0rg0 and the corresponding register buffer are mapped to the same address (0xffff_f18a and 0xffff_f18b). when tb0run.tb0rde = 0, a time constant value is written to both the tb0rg0 and the register buffer; when tb0r un.tb0rde = 1, a time constant valu e is written only to the register buffer. therefore, the double-buffering function shoul d be disabled when writing an initial time constant to the timer register. TMP1962C10BXBG 2006-02-21 tmp1962-243 12.2.4 capture registers (tb0cp0h/l and tb0cp1h/l) the capture registers are 16-bit registers used to latch the value of the up-counter (uc0). each of the capture registers can be read with either a halfword-load instruction or a series of two byte-load instructions. when byte-load instructions are used, the low-order byte must be read first, followed by the high-order byte. 12.2.5 capture control logic the capture control logic controls the capture of an up-counter (uc0) value into the capture registers (tb0cp0 and tb0cp1). the tb0cpm[1:0] field in the tb0mod register selects a capture trigger input to be sensed by the capture control logic. furthermore, a counter value can be captured under software control; a write of 0 to the tb0mod.tb0cp0 bit causes the current uc0 value to be latched into the tb0cp0. to use the capture capability, the prescaler must be running (i.e., tb0run.tb0prun=1). in 2-phase pulse count mode (for the tmrb2 and tmrb3 only), the counter value is captured under software control. 12.2.6 comparators (cp0 and cp1) the tmrb0 contains two 16-bit comparators. the cp0 block compares the output of the up-counter (uc0) with a time constant value in the tb0rg0. the cp1 block compares the output of the uc0 with a time constant value in the tb0rg1. when a match is detected, an interrupt (inttb0) is generated. 12.2.7 timer flip-flop (tb0ff0) the timer flip-flop (tb0ff0) is togg led, if so enabled, upon assertion of match-detect signals from the comparators and latch signals from the capture control logic. the toggling of the tb0ff0 can be enabled and disabled through the programming of the tb0c1t1, tb0c0t1, tb0e1t1 and tb0e0t1 bits in the tb0ffcr register. upon reset, the tb0ff0 assumes an undefined state. the tb0ff0 can be initialized to 1 or 0 by writing 01 or 10 to the tb0ff0c[1:0] field in the tb0ffcr. a write of 01 to this field sets the tb0ff0; a write of 10 to this field clears the tb0ff0. additionally, a write of 00 causes the tb0ff0 to be toggled to the opposite value. the value of the tb0ff0 can be driven onto the tb0out pin, which is multiplexed with pb0. the port b registers (pbcr and pbfc) must be programmed to configure the pb0/tb0out pin as tb0out. note 1: reading the eight low-order bits of a capture register disables the capture capability. reading the eight high-order bits thereafter re-enables the capture capability. note 2: do not stop the timer after only reading the eight low- order bits of a capture register. if this is done, the capture capability continues to remain in the disabled state even after the timer is restarted. TMP1962C10BXBG 2006-02-21 tmp1962-244 12.3 register description tmrbn run register (n = 0 or 1) 7 6 5 4 3 2 1 0 bit symbol tbnrde ? i2tbn tbnprun tbnrun read/write r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 0 function double- buffering 0: disable 1: enable must be written as 0. must be written as 0. idle 0: off 1: on timer run/stop control 0: stop & clear 1: run tbnrun: runs or stops the tmrbn. tbnprun: runs or stops the tmrbn prescaler. i2tbn: enables or disables the operation of the tmrbn in idle mode. tbnrde: enables or disables double-buffering. tmrbn run register (m = 2 or 3) 7 6 5 4 3 2 1 0 bit symbol tbmrde ? udmck tbmudce i2tbm tbmprun tbmrun read/write r/w r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 0 0 function double- buffering 0: disable 1: enable must be written as 0. must be written as 1. 2-phase counter enable 0: disable 1: enable idle 0: off 1: on timer run/stop control 0: stop & clear 1: run tbmrun: runs or stops the tmrbm. tbmprun: runs or stops the tmrbm prescaler. i2tbm: enables or disables the op eration of the tmrbm in idle mode. tbmudce: enables or disables the 2-phase pulse input count function. udmck: selects the sampling clock for the 2-phase pulse input count function. tbmrde: enables or disables double-buffering. figure 12.3 tmrb registers tbnrun (0xffff_ f1x3) tbmrun (0xffff_ f1x3) note: bits 1 and 5 of the tbnrun are read as 0. note 1: bit 1 of the tbmrun is read as 0. note 2: when bit 4 of the tbmrun is set to 1, the tmrbm enters 2-phase pulse input count mode and the counter operates as an up/down counter. when the bit is cleared to 0, the tmrbm enters normal timer mode and the counter operates as an up-counter only. TMP1962C10BXBG 2006-02-21 tmp1962-245 tmrbn control register (n = 0 to 3) 7 6 5 4 3 2 1 0 bit symbol tbnen ? read/write r/w r/w reset value 0 0 function tmrbn operation 0: disable 1: enable must be written as 0. tbnen: enables or disables the operation of the tmrbn. if the tmrbn is disabled, no clock pulses are supplied to the tmrbn registers other than the tbncr, so that power consumption in the system can be reduced (only the tbncr can be read or written). to use the tmrbn, set the tbnen bit to 1 before configuring other registers of the tmrbn. once the tmrbn operates, all settings in its registers are held if it is disabled. tmrbn mode register (n = 0 to 3) 7 6 5 4 3 2 1 0 bit symbol ? ? tbncp0 tbncpm1 tbncpm0 tbncle tbnclk1 tbnclk0 read/write w r/w reset value 0 0 1 0 0 0 0 0 function must be written as 00. software capture 0: capture 1: don't care capture triggers 00: disabled 01: tbnin0 tbnin1 10: tbnin0 tbnin0 11: ta3out ta3out up- counter clear control 0: disable 1: enable clock source 00: tbnin0 input 01: t0 10: t2 11: t8 tbnclk[1:0]: selects the clock source for the tmrbn. tbncle: enables or disables the clearing of the tmrbn up-counter. 0: disables clearing. 1: enables the up-counter to be cleared upon a match with tbnrg1. tbncpm[1:0]: specifies the tmrbn capture timing. 00: disables the capture function. 01: latches the counter value into capture register 0 (tbncp0) at rising edges of tbnin0. latches the counter value into capture register 1 (tbncp1) at rising edges of tbnin1. 10: latches the counter value into capture register 0 (tbncp0) at rising edges of tbnin0. latches the counter value into capture register 1 (tbncp1) at falling edges of tbnin0. 11: latches the counter value into capture register 0 (tbncp0) at rising edges of ta3out (8-bit timer match output). latches the counter value into capture register 1 (tbncp1) at falling edges of ta3out. tmrb0 to 3: ta3out tbncp0: writing 0 to this bit latches the count er value into capture register 0 (tbncp0). figure 12.4 tmrb registers tbnmod (0xffff_ f1x1) tbncr (0xffff_ f1x2) note: bits 0 to 5 of the tbncr are read as 0. note: bit 5 of the tbnmod is read as 1. TMP1962C10BXBG 2006-02-21 tmp1962-246 tmrbn flip-flop control register (n = 0 to 3) 7 6 5 4 3 2 1 0 bit symbol ? ? tbnc1t1 tbnc0t1 tbne1t1 tbne0t1 tbnff0c1 tbnff0c0 read/write w * r/w w * reset value 1 1 0 0 0 0 1 1 tbnff0 toggle trigger 0: trigger disabled 1: trigger enabled function must be written as 11. * this field is always read as 11. when the up-counter value is latched into tbncp1 when the up-counter value is latched into tbncp0 when the up-counter value reaches tbnrg1 when the up-counter value reaches tbnrg0 tbnff0 control 00: invert 01: set 10: clear 11: don?t care * this field is always read as 11. tbnff0c[1:0]: controls the timer flip-flop. 00: toggles tbnff0. (software toggle) 01: sets tbnff0 to 1. 10: clears tbnff0 to 0. 11: don't care. tbne[1:0]: enables or disables the toggling of the timer-flip flop when the up-counter value reaches the value stored in time r register 0 or 1 (tbnrg0/1). tbnc[1:0]: enables or disables the toggling of the timer-flip flop when the up-counter value is latched into capture register 0 or 1 (tbncp0/1). figure 12.5 tmrb registers tbnffcr (0xffff_ f1x0) TMP1962C10BXBG 2006-02-21 tmp1962-247 tmrbn status register (n = 0 or 1) 7 6 5 4 3 2 1 0 bit symbol inttbofn inttbn1 inttbn0 read/write r reset value 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated inttbn0: timer register 0 (tbnrg0) match-detected interrupt inttbn1: timer register 1 (tbnrg1) match-detected interrupt inttbofn: up-counter overflow interrupt tmrbm status register (m = 2 or 3) (1) when tbmrun.tbmudce = 0: normal timer mode 7 6 5 4 3 2 1 0 bit symbol inttbofm inttbm1 inttbm0 read/write r reset value 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated inttbm0: timer register 0 (tbmrg0) match-detected interrupt inttbm1: timer register 1 (tbmrg1) match-detected interrupt inttbofm: up-counter overflow interrupt tbnst (0xffff_ f1x7) tbmst (0xffff_ f1x7) note: when an interrupt occurs, the corresponding flag in the tbnst is set and the intc is notified of the interrupt. reading the tbnst register results in all its flags being cleared. note: when an interrupt occurs, the corresponding flag in the tbmst is set and the intc is notified of the interrupt. reading the tbmst register results in all its flags being cleared. TMP1962C10BXBG 2006-02-21 tmp1962-248 (2) when tbmrun.tbmudce = 1: 2-phase pulse input count mode 7 6 5 4 3 2 1 0 bit symbol inttbudm inttbudfm inttboufm read/write r reset value 0 0 0 function up/down count 0: no count 1: count (in- cremented or de- cremented) underflow 0: no underflow 1: underflow overflow 0: no overflow 1: overflow inttbovfm: up/down counter overflow interrupt inttbudfm: up/down counter underflow interrupt inttbudm: up- or down-count interrupt figure 12.6 tmrb registers tbmst (0xffff_ f1x7) note: when an interrupt occurs, the corresponding flag in the tbmst is set and the intc is notified of the interrupt. reading the tbmst register results in all its flags being cleared. TMP1962C10BXBG 2006-02-21 tmp1962-249 12.4 operating modes 12.4.1 16-bit interval timer mode in the following example, the tmrb0 is used to accomplish periodic interrupt generation. the interval time is set in timer register 1 (tb0rg1) , and the inttb01 interrupt is enabled. 7 6 5 4 3210 tb0run 0 0 x 0 ? 0 x 0 stops the tmrb0. imc7lh x x 1 1 0100 e nables inttb0 and sets its priority level to 4. tb0ffcr 1 1 0 0 0011 disables the timer flip-flop toggle trigger. tb0mod 0 0 1 0 0 1 * * selects a prescaler output clock as the timer clock source ( ** = 01, 10, 11) and disables the capture function. tb0rg1 * * * * * * * * sets the interval time * * * * * * * * (16 bits). tb0run 0 0 x 0 ? 1 x 1 starts the tmrb0. x = don't care, - = no change 12.4.2 16-bit event counter mode this mode is used to count events by interpreting the rising edges of the external counter clock (tb0in0) as events. the up-counter counts up on each ri sing clock edge. the counter value can be latched into a capture register under software control. to determine the numb er of events (i.e., cycles) counted, the value in the capture register must be read. 7 6 5 4 3210 tb0run 0 0 x 0 ? 0 x 0 stops the tmrb0. plcr ? ? ? 0 ? ? ? ? plfc ? ? ? 1 ? ? ? ? configures the pl4 pin for input mode. imc7lh x x 1 1 0100 e nables inttb0 (interrupt level = 4). tb0ffcr 1 1 0 0 0011 disables the timer flip-flop toggle trigger. tb0mod 0 0 1 0 0100 selects the tb0in0 input as the timer clock source. tb0rg1 * * * * * * * * sets a count value (16 bits). tb0run 0 0 x 0 ? 1 x 1 starts the tmrb0. x = don't care, - = no change even when the timer is used for event counting, the prescaler must be programmed to run (i.e., the tb0run.tb0prun bit must be set to 1). TMP1962C10BXBG 2006-02-21 tmp1962-250 12.4.3 16-bit programmable pulse generation (ppg) mode the 16-bit ppg mode can be used to generate a square wave with any frequency and duty cycle. the pulse can be high-going and low-going, as determined by the initial setting of the timer flip-flop (tb0ff). a square wave is generated by toggling the timer f lip-flop every time the up-counter uc0 reaches the values in each timer register (tb0rg0 and tb0rg1). the square-wave output is driven to the tb0out pin. in this mode, the following relationship must be satisfied: (tb0rg0 value) < (tb0rg1 value) tb0rg0 match (inttb00 interrupt) tb0rg1 match (inttb01 interrupt) tb0out pin figure 12.7 ppg output waveform if the double-buffering function is enabled, the tb0rg0 value can be changed dynamically by writing a new value into the register buffer. upon a match between the tb0rg1 and the uc0, the tb0rg0 latches a new value from the register buffer. the tb0rg0 can be loaded with a new value upon every match, thus making it easy to generate a square wave with virtually any duty cycle. q 1 q 2 q 2 q 3 shift into tb0rg1 up-counter = q 1 up-counter = q 2 tb0rg0 match tb0rg1 match tb0rg0 (compare value) re g ister buffer write to tb0rg0 figure 12.8 register buffer operation TMP1962C10BXBG 2006-02-21 tmp1962-251 figure 12.9 shows a functional diagram of 16-bit ppg mode. selector selector tb0run TMP1962C10BXBG 2006-02-21 tmp1962-252 12.4.4 timing and measurement functions using the capture capability the capture capability of the tmrbn provides versatile timing and measurement functions, including the following: (1) one-shot pulse generation using an external trigger pulse (2) frequency measurement (3) pulse width measurement (4) time difference measurement ? one-shot pulse generation using an external trigger pulse the tmrbn can be used to produce a one-time pulse as follows. the 16-bit up-counter (uc2) is programmed to function as a free-running counter, clocked by one of the prescaler outputs. the tb2in0 pin is used as an active-high external trigger pulse input for latching the counter value into capture register 0 (tb2cp0). the interrupt controller (intc) must be prog rammed to generate an int5 interrupt upon detection of a rising edge on the tb2in0 pin. a one-shot pulse has a delay and width controlled by the values stored in the timer registers (tb2rg0 and tb2rg1). programming the tb2rg0 and tb2rg1 is the responsibility of the int5 interrupt handler. the tb2rg0 is loaded with the sum of the tb2cp0 value (c) plus the pulse delay (d) ? i.e., (c) + (d). the tb2rg1 is loaded with the sum of the tb2rg0 value plus the pulse width (p) ? i.e., (c) + (d) + (p). next, the tb2e1t1 and tb2e0t1 bits in the timer flip-flop control register (tb2ffcr) are set to 11, so that the timer flip-flop (tb2ff0) will toggle when a match is detected between the uc2 and the tb2rg0 and between the uc2 and the tb2rg1. with the tb2ff0 toggled twice, a one-shot pulse is produced. upon a match between the uc2 and the tb2rg1, the tmrb2 generates the inttb2 interrupt, which must disable the toggle trigger for the tb2ff0. figure 12.10 depicts one-shot pulse generation, with annotations showing (c), (d) and (p). tb2out (timer output) pin c + d + p c + d c toggle is disabled for a capture into tb2cp1. toggle is enabled. (p) (d) pulse width delay toggle is enabled. inttb2 is generated. the uc2 value is latched into tb2cp1. int5 is generated. counter clock (internal clock) the counter is free-running. tb2in0 input pin (external trigger pulse) tb2rg0 match tb2rg1 match inttb2 is generated. figure 12.10 one-shot pulse generation (with a delay) TMP1962C10BXBG 2006-02-21 tmp1962-253 example: generating a one-shot pulse with a width of 2 ms and a delay of 3 ms on assertion of an external trigger pulse on the tb2in0 pin clocking conditions: system clock: high-speed (fc) high-speed clock gear: x1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) settings in the main routine places the counter in free-running mode. 7 6 5 4 3210 selects t0 as the counter clock source. tb2mod x x 1 0 1001 latches uc2 va lue into tb2cp0 at rising edges of the tb2in0 input. tb2ffcr x x 0 0 0010 clears tb2ff0 to 0. disables the toggle trigger for tb2ff0. pbcr ? - ? 1 ? ? ? pbfc ? - ? 1 ? ? ? configures the pb4 pin as tb2out. imc2hl x x 1 1 0100 imcclh x x 1 1 0000 enables int5 and disables inttb2. tb2run ? 0 x 0 ? 1 x 1 starts the tmrb2. settings in int5 tb2rg0 tb0cp0 + 3ms/ t1 tb2rg1 tb0rg0 + 2ms/ t1 tb2ffcr x x ? ? 11 ? ? enables the tb2ff0 toggle trigger for tb2rg0 and tb2rg1 matches. imcclh x x 1 1 0100 e nables inttb2. settings in inttb2 tb2ffcr x x ? ? 00 ? ? disables the tb2 ff0 toggle trigger for tb2rg0 and tb2rg1 matches. imcclh x x 1 1 0000 disables inttb2. x = don't care, - = no change if no delay is necessary, enable the tb2ff0 toggle trigger for a capture of the uc2 value into the tb2cp0. use the int5 interrupt to load the tb2rg1 with a sum of the tb2cp0 value (c) plus the pulse width (p) and to enable the tb2ff0 toggle trigger for a match between the uc2 and tb2rg1 values. a match generates the inttb2 interrupt, which then is to disable the tb2ff0 toggle trigger. TMP1962C10BXBG 2006-02-21 tmp1962-254 c + p c toggle is enabled. (p) pulse width the uc2 value is latched into tb2cp0. int5 is generated. counter clock (prescaler output clock) tb2in0 input (external trigger pulse) tb2rg1 match tb2out (timer output) pin the uc2 value is latched into tb2cp1. inttb2 is generated. toggle is enabled for a capture into tb2cp0. toggle is left disabled for a capture into tb2cp1 so that it will not be toggled. figure 12.11 one-shot pulse generation (without a delay) ? frequency measurement the capture function can be used to measure the frequency of an external clock. frequency measurement requires a 16-bit tmrbn channel running in event counter mode and the 8-bit tmra01. the timer flip-flop (ta1ff) in the tmra01 is used to define the duration during which a measurement is taken. select the tb0in0 pin as the clock source for the tmrb0. set the tb0cpm[1:0] field in the tb0mod to 11 to select the ta1ff output signal from the tmra01 as a capture trigger input. this causes the tmrb0 to latch the 16-bit up-counter (uc0) value into capture register 0 (tb0cp0) on the low-to-high transition of the ta1ff and into capture register 1 (tb0cp1) on the next high-to-low transition of the ta1ff. either the intta0 or intta1 interrupt generated by the 8-bit timer can be used to make a frequency calculation. c2 c1 c2 c1 c2 c1 counter clock (tb0in0 input) ta1out capture into tb0cp0 capture into tb0cp1 intta0/intta1 figure 12.12 frequency measurement for example, if the ta1ff of the 8-bit timer is programmed to be at logic 1 for a period of 0.5 seconds and the difference between the values captured into the tb0cp0 and tb0cp1 is 100, then the tb0in0 frequency is calculated as 100 0.5 s = 200 hz. TMP1962C10BXBG 2006-02-21 tmp1962-255 ? pulse width measurement the capture function can be used to measure the pu lse width of an external clock. the external clock is applied to the tb2in0 pin. the up-counter (uc2) is programmed to operate as a free-running counter, clocked by one of the pres caler outputs. the capture function is used to latch the uc2 value into capture register 0 (tb2cp0) at the clock rising edge and into capture register 1 (tb2cp1) at the next clock falling edge. an int5 interrupt is generated at the falling edge of the tb2in0 input. multiplying the counter clock period by the difference between the values captured into the tb2cp0 and tb2cp1 gives the high pulse width of the tb2in0 clock. for example, if the prescaler output clock has a period of 0.5 s and the difference between the tb2cp0 and tb2cp1 is 100, the high pulse width is calculated as 0.5 s x 100 = 50 s. measuring a pulse width exceeding the maximum counting time for the uc2, which depends on the clock source, requires software programming. c2 c1 c2 c1 c2 c1 prescaler output clock tb2in0 input (external clock) capture into tb2cp0 int5 capture into tb2cp1 figure 12.13 pulse width measurement the low pulse width can be measured by the second int5 interrupt. this is accomplished by multiplying the counter clock period by the difference between the tb2cp0 value at the first c2 and the tb2cp1 value at the second c1. TMP1962C10BXBG 2006-02-21 tmp1962-256 ? time difference measurement the capture function can be used to measure th e time difference between two event occurrences. the 16-bit up-counter (uc2) is programmed to operate as a free-running counter. the uc2 value is latched into capture register 0 (tb2cp0) on the rising edge of tb2in0. an int5 interrupt is generated at this time. then, the uc2 value is latched into capture register 1 (tb2cp1) on the rising edge of tb2in1. an int6 interrupt is ge nerated at this time. the time difference between the two events that occurred on the tb2in0 and tb2in1 pins is calculated by multiplying the counter clock period by the difference between the tb2cp1 and tb2cp0 values. time difference c2 c1 tb2in0 input tb2in1 input int5 capture into tb2cp0 int6 capture into tb2cp1 prescaler output clock figure 12.14 time difference measurement TMP1962C10BXBG 2006-02-21 tmp1962-257 12.4.5 2-phase pulse input count mode (tmrb2 and tmrb3) the tmrb2 and tmrb3 are functionally equivalent. this section only describes the tmrb2. in 2-phase pulse input count mode, the counter oper ates as an up/down coun ter that increments and decrements according to transitions in the states of 2-phase cloc ks, input through the tb2in0 and tb2in1 pins. an interrupt occurs when the counter increments or decrements, or when it overflows or underflows. (1) count operation ? increment figure 12.15 when the counter increments ? decrement figure 12.16 when the counter decrements tmrb2 run register (tb2run) 7 6 5 4 3 2 1 0 bit symbol tb2rde ud2ck tb2udce i2tb2 tb2prun tb2run read/write r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 0 function double- buffering 0: disable 1: enable sampling clock 0: setting prohibited 1: fsys/2 2-phase counter enable 0: disable 1: enable idle 0: off 1: on timer run/stop control 0: stop & clear 1: run (count up) figure 12.17 2-phase pulse input count mode register 1 1 counter value incremented by one tb0in0 tb0in1 01 n + 1 counter value counter value decremented by one tb0in0 tb0in1 0 1 n counter value n - 1 1 1 TMP1962C10BXBG 2006-02-21 tmp1962-258 setting the bit 5 (ud2ck) of the tb2run register to 1 specifies the sampling clock frequency. ud2ck (sampling clock) = 1 : fsys/2 (fsys/8-hz sampling) exiting stop mode when the tmp1962 enters stop mode, the 2-ph ase counter holds the current status. if the combination of the held status and the status of inputs used for terminating stop mode satisfies the increment or de crement conditions, th e counter increments or decrements when the tmp1962 exits stop mode. if a fixed status is required after recovery from stop mode, initialize the 2-phase counter to 0x7fff once the tmp1962 exits stop mode, by clearing the tb2run.tb2ucde bit to 0 and then re-setting it to 1. (2) operating mode whether external signals input through the tb2in0 and tb2in1 pins are directed to the regular 16-bit timer (capture input) or the up/down counter depends on register settings. ? in up/down counter mode, only software capture is available. the timer cannot capture data based on external clock timing. ? in up/down counter mode, the comparator is disabl ed; comparison with the timer register is not performed. ? input clock sampling is based clock (system clock). the maximum input frequency is fsys/16 hz . enabling the up/down counter clear the tb2clk[0:1] bits of the tb2mod register to 00, thus turn ing the prescaler off. then, use bit 4 (tb2udce) of the tb2run regi ster to specify whether the counter will operate as an up/down counter or a normal up-counter. tb2udce (up/down counter enable) = 0: normal 16-bit timer operation = 1: up/down counter operation tmrb2 run register (tb2run) 7 6 5 4 3 2 1 0 bit symbol tb2rde ud2ck tb2udce i2tb2 tb2prun tb2run read/write r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 0 function double- buffering 0: disable 1: enable sampling clock 0: setting prohibited 1: fsys/2 2-phase counter enable 0: disable 1: enable idle 0: off 1: on timer run/stop control 0: stop & clear 1: run (count up) figure 12.18 up/down counter enable bit TMP1962C10BXBG 2006-02-21 tmp1962-259 (3) interrupts ? normal mode enable the inttb2 interrupt in the interrupt co ntroller (intc). an inttb2 interrupt occurs when the counter increments or decrements. the interrupt serv ice routine can read the tmrb2 status register (tb2st) to determine whether an overflow or underflow has occurred. if an overflow occurs, the inttbouf2 bit of the tb2st register is set to 1. if an underflow occurs, the inttbudf2 bit of the tb2st register is set to 1. reading the tb2st register clears all of its bits. an overflow causes the counter value to be 0x0000 and an underflow causes the counter value to be 0xffff. in eith er case, counting continues. 7 6 5 4 3 2 1 0 bit symbol inttbud2 inttbudf2 inttbouf2 read/write r reset value 0 0 0 function up/down count 0: no count 1: count (in- cremented o r de- cremented) underflow 0: no underflow 1: underflow overflow 0: no overflow 1: overflow figure 12.19 tmrb2 status register ? stop mode in stop mode, the 2-phase pulse input counter is stopped. enable the int5 or int6 for stop wake-up signaling in the clock generator (cg). when the counter increm ents or decrements, an int5 or int6 interrupt occurs, causing the tmp1962 to exit stop mode. upon recovery from stop mode, the tmp1962 enters normal or slow mode after a specified warm-up time, restarting the counter. if the combination of th e held status and the status of inputs used for terminating stop mode satisfies the increment or decrement conditions, the counter increments or decrements. tb2st (0xffff_ f167) TMP1962C10BXBG 2006-02-21 tmp1962-260 (4) up/down counter when 2-phase pulse input count mode is sel ected (tb2run.tb2ucde = 1), the up-counter operates as an up/down counter and is initialized to 0x7fff. when the counter overflows, it is reset to 0x0000 and continues counting. when the counter underflows, it is reset to 0xffff and continues counting. once an interrupt occurs, the interrupt service routine can determine the overflow or underflow status by reading the counter value and the status flags in the tb2st. increment input up/down counter value up/down counter interrupt sampling clock 0x3fff 0x4000 0x4001 note 1: the increment or decrement input must be high before and after effective input. note 2: the counter value must be read in the inttb2 interrupt service routine. if it is read in the int5 or int6 interrupt routine used for stop wake-up signaling, the value may vary depending on whether the increment/decrement conditions are satisfied or on the delay between recovery from stop mode and the start of counting. TMP1962C10BXBG 2006-02-21 tmp1962-261 13. 32-bit input capture (tmrc) the tmp1962 contains a 32-bit input capture circuit bloc k (tmrc), which consists of a 1-channel 32-bit time base timer (tbt), eight 32-bit input capture regist ers (tccap0-tccap7) and eigh t 32-bit compare registers (tccmp0-tccmp7). figure 13.1 shows a block diagram of the tmrc. 13.1 tmrc block diagram figure 13.1 tmrc block diagram noise eliminator 32-bit time base timer (tbt) overflow interrupt (inttbt) clear & count control noise eliminator edge detection 32-bit input capture (tccap0) capture 0 interrupt (intcap0) capture registers 0-7 (tccap0-tccap7) prescaler clock source ( t0) run & clear 32-bit comparator 32-bit compare register 0 (tccmp0) 32-bit register buffer 0 compare match interrupt 0 (intcmp0) compare match trigger (cmp0trg) compare registers 0-7 (tccmp0-tccmp7) compare match output (tcout0) prescaler output ( t0- t128) tbtin (pm0) tc0in (pm1) 2 4 8 16 32 64 128 256 t1 t2 t4 t8 t16 t32 t64 t128 TMP1962C10BXBG 2006-02-21 tmp1962-262 13.2 timer components 13.2.1 prescaler the tmrc has an 8-bit prescaler that slows the rate of a clocking source to the timer. the prescaler clock source ( t0) can be selected from fperiph/4, fperiph/8 and fperiph/16 by programming the prck[1:0] field of the syscr0 located within the cg. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the fpsel bit of the syscr1 located within the cg. the tbtprun bit in the tbtrun register allows th e enabling and disabling of the prescaler for the tmrc. a write of 1 to this bit starts the prescaler. a write of 0 to this bit clears and halts the prescaler. table 13.1 shows prescaler output clock resolutions. table 13.1 prescaler output clock resolutions @fc = 40.5 mhz prescaler output clock resolution peripheral clock source fpsel clock gear value gear[1:0] prescaler clock source prck[1:0] t1 t2 t4 t8 0(fgear) 00(fc) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) 01(fperiph/8) fc/2 4 (0.40 s) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) 10(fperiph/4) fc/2 3 (0.20 s) fc/2 4 (0.40 s) fc/2 5 (0.79 s) fc/2 6 (1.58 s) 01(fc/2) 00(fperiph/16) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) 01(fperiph/8) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) 10(fperiph/4) fc/2 4 (0.40 s) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) 10(fc/4) 00(fperiph/16) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) 01(fperiph/8) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) 10(fperiph/4) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) 11(fc/8) 00(fperiph/16) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) 01(fperiph/8) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) 10(fperiph/4) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) 1(fc) 00(fc) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) 01(fperiph/8) fc/2 4 (0.40 s) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) 10(fperiph/4) fc/2 3 (0.20 s) fc/2 4 (0.40 s) fc/2 5 (0.79 s) fc/2 6 (1.58 s) 01(fc/2) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) 01(fperiph/8) fc/2 4 (0.40 s) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) 10(fperiph/4) fc/2 3 (0.20 s) fc/2 4 (0.40 s) fc/2 5 (0.79 s) fc/2 6 (1.58 s) 10(fc/4) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) 01(fperiph/8) fc/2 4 (0.40 s) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) 10(fperiph/4) ? fc/2 4 (0.40 s) fc/2 5 (0.79 s) fc/2 6 (1.58 s) 11(fc/8) 00(fperiph/16) fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) fc/2 8 (6.32 s) 01(fperiph/8) ? fc/2 5 (0.79 s) fc/2 6 (1.58 s) fc/2 7 (3.16 s) 10(fperiph/4) ? ? fc/2 5 (0.79 s) fc/2 6 (1.58 s) TMP1962C10BXBG 2006-02-21 tmp1962-263 @fc = 40.5 mhz prescaler output clock resolution peripheral clock source fpsel clock gear value gear[1:0] prescaler clock source prck[1:0] t16 t32 t64 t128 0(fgear) 00(fc) 00(fperiph/16) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) 01(fperiph/8) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) 10(fperiph/4) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) 01(fc/2) 00(fperiph/16) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) fc/2 13 (202 s) 01(fperiph/8) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) 10(fperiph/4) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) 10(fc/4) 00(fperiph/16) fc/2 11 (50.6 s) fc/2 12 (101 s) fc/2 13 (202 s) fc/2 14 (405 s) 01(fperiph/8) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) fc/2 13 (202 s) 10(fperiph/4) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) 11(fc/8) 00(fperiph/16) fc/2 12 (101 s) fc/2 13 (202 s) fc/2 14 (405 s) fc/2 15 (809 s) 01(fperiph/8) fc/2 11 (50.6 s) fc/2 12 (101 s) fc/2 13 (202 s) fc/2 14 (405 s) 10(fperiph/4) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) fc/2 13 (202 s) 1(fc) 00(fc) 00(fperiph/16) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) 01(fperiph/8) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) 10(fperiph/4) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) 01(fc/2) 00(fperiph/16) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) 01(fperiph/8) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) 10(fperiph/4) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) 10(fc/4) 00(fperiph/16) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) 01(fperiph/8) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) 10(fperiph/4) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) 11(fc/8) 00(fperiph/16) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) fc/2 12 (101 s) 01(fperiph/8) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) fc/2 11 (50.6 s) 10(fperiph/4) fc/2 7 (3.16 s) fc/2 8 (6.32 s) fc/2 9 (12.6 s) fc/2 10 (25.3 s) note 1: the prescaler's output clock tn must be selected so that the relationship tn < fsys/2 is satisfied. note 2: do not change the clock gear value while the timer is running. note 3: the - character means "setting prohibited." TMP1962C10BXBG 2006-02-21 tmp1962-264 13.2.2 noise eliminator the noise eliminator removes noise components fr om the external clock source (tbtin) and capture trigger input (tcnin) for the time ba se timer (tbt). it can also output the input signals as is, without eliminating noise. 13.2.3 32-bit time base timer (tbt) the tmrc contains a 32-bit binary counter, which counts up on the rising edge of a clock selected by the tbtclk[3:0] field in the tbt control register (tbtcr). the clock input to the tbt is either one of eight prescaler outputs ( 1, t2, 4, t8, 16, t32, 64, t128) or the external clock applied to the tbtin pin. the tbtrun bit in the tbtrun register is used to start the tbt and to stop and clear the tbt. upon reset, the tbt is cleared and stopped. when started, the tbt acts as a free-running counter. an overflow interrupt (inttbt) is generated upon a counter overfl ow and clears the counter to 0, after which the counter restarts counting. inttbt is grouped with other interrupt sources and controlled in the tcg1st and tcg1im registers, in the same way as intcapn described in section 13.2.5. 13.2.4 edge detection circuit this circuit samples the external capture input (tcnin) and detects its edges. the cpneg[1:0] field in the capture control register (capncr) defines the edge detection polarity: rising edge, falling edge, both edges or no capture. figure 13.2 shows the relationship between the capture input and the output from the edge detection circuit (capture source output). figure 13.2 capture input and capture source output (output from the edge detection circuit) tcnin input capture source (when rising edges are detected) (when falling edges are detected) (when both edges are detected) (when the input is not captured) TMP1962C10BXBG 2006-02-21 tmp1962-265 13.2.5 32-bit capture registers the tmrc contains 32-bit registers to which the tbt counter value is captured in response to a capture trigger source. a capture interrupt (intca pn) occurs when the counter value is captured. intcap0 to intcap3 are handled as a group so that any of the four interrupt sources are sent to the intc as the same interrupt source. the interrupt service routine can determ ine the actual source by reading the status register (tcg0st). unnecessary interrupt requests can be masked by setting corresponding bits in the interrupt mask register (tcg0im). any capture trigger does not cause the counter value to be captured while the capture register is being read. 13.2.6 32-bit compare registers the tmrc contains eight 32-bit re gisters (tccmp0-tccmp7) in whic h compare values are stored. when the tbt value reaches the va lue stored in a compare register , the comparator activates the corresponding match-detected si gnal. the cmpen[1:0] field in the compare control register (cmpctl) allows the enabling and disabling of comparison. tccmpn can be written with either a word-store instruction, a series of two halfword-store instructions or a series of four byte-store instructio ns. when halfword-store or byte-store instructions are used, the low-order byte must be stored first, followed by the high-order byte. each of the compare registers (tccmpn) is d ouble-buffered with register buffer n. the double-buffering function can be enabled and disabled through the programming of the cmprden bit in the cmpctl register: 0 = disable, 1 = enable. if double-buffering is enabled, the tccmpn latches a new compare value from register buffer n. this takes place when a match is detected between the tbt and the tccmpn. upon reset, the contents of the tccmpn are undefine d; thus, they must be loaded with valid values before the timer can be used. a reset clears the cmpctl.cmprden bit to 0, disabling the double-buffering function. to use this function, the cmpctl.cmprden bit must be set to 1 after loading the tccmpn with compare values. when cm pctl.cmprden = 1, the next compare value can be written to register buffer n. the tccmpn and the corresponding register bu ffer are mapped to the same address. when cmpctl.cmprden = 0, a compare value is written to both the tccmpn and the register buffer; when cmpctl.cmprden = 1, a compare value is written on ly to the register buffer. therefore, the double-buffering function should be disabled when writing an initial compare value to a compare register. TMP1962C10BXBG 2006-02-21 tmp1962-266 13.3 register description tmrc control register 7 6 5 4 3 2 1 0 bit symbol tcen i2tbt read/write r/w reset value 0 0 function tmrc operation 0: disable 1: enable idle 0: off 1: on i2tbt: enables or disables the operation of the tmrc in idle mode. tcen: enables or disables the operation of the tmrc. if the tmrc is disabled, no clock pulses are supplied to the tmrc registers other than the tccr, so that power consumption in the system can be reduced (only the tccr can be read or written). to use the tmrc, set the tcen bit to 1 before configuring other registers of the tmrc. once the tmrc operates, all settings in its registers are held if it is disabled. tbtrun register 7 6 5 4 3 2 1 0 bit symbol tbtcap tbtprun tbtrun read/write w r/w reset value 0 0 0 0 function must be written as 0. tbt counter soft capture 0: don't care 1: soft capture timer run/stop control 0: stop & clear 1: run tbtrun: runs or stops the tbt. tbtprun: runs or stops the tbt prescaler. tbtcap: setting this bit to 1 causes the tbt counter value to be captured into the capture register (tbtcapn). figure 13.3 tmrc registers tccr (0xffff_f403) note: bits 0 to 6 of the tccr are read as 0. tbtrun (0xffff_f402) TMP1962C10BXBG 2006-02-21 tmp1962-267 tbt control register 7 6 5 4 3 2 1 0 bit symbol tbtnf tbtclk3 tbtclk2 tbtclk1 tbtclk0 read/write r/w reset value 0 0 0 0 0 0 0 0 function tbtin input noise elimination 0: not eliminated 1: eliminated must be written as 0. tbt clock source 0000: t1 0001: t2 0010: t4 0011: t8 0100: t16 0101: t32 0110: t64 0111: t128 1xxx: tbtin input tbtclk[3:0]: selects the tbt clock source. when tbtclk[3:0] = 0000 to 0111, a prescaler output is used. when tbtclk[3:0] = 1xxx, a clock input through the tbtin pin is used. tbtnf: controls whether noise will be eliminated from the signal input through the tbtin pin. when tbtnf = 0, the tbtin input is direc tly used as the tbt clock source. when tbtnf = 1, high and low levels on tbtin shor ter than 4/fsys (99 ns @fperiph = fc = 40.5 mhz) are regarded as noise and el iminated from the input. the elimination threshold varies with the clock gear setting. tbt capture register (tbtcap) 31 30 29 28 27 26 25 24 bit symbol cap031 cap030 cap029 cap028 cap027 cap026 cap025 cap024 read/write r reset value function capture data 23 22 21 20 19 18 17 16 bit symbol cap023 cap022 cap021 cap020 cap019 cap018 cap017 cap016 read/write r reset value function capture data 15 14 13 12 11 10 9 8 bit symbol cap015 cap014 cap013 cap012 cap011 cap010 cap09 cap08 read/write r reset value function capture data 7 6 5 4 3 2 1 0 bit symbol cap07 cap06 cap05 cap04 cap03 cap02 cap01 cap00 read/write r reset value function capture data figure 13.4 tmrc registers tbtcr (0xffff_f401) tbtcap3 (0xffff_f404) tbtcap2 (0xffff_f405) tbtcap1 (0xffff_f406) tbtcap0 (0xffff_f407) TMP1962C10BXBG 2006-02-21 tmp1962-268 tmrc capture 0 control register 7 6 5 4 3 2 1 0 bit symbol tc0nf cp0eg1 cp0eg0 read/write r/w r/w reset value 0 0 0 function tc0in input noise elimination 0: not eliminated 1: eliminated tc0in edge detection 00: not captured 01: rising edge 10: falling edge 11: both edges cp0eg[1:0]: selects the edge to be detected on the tc0in pin for the tccap0. when cp0eg[1:0] = 00, capture is disabled for the tccap0. tc0nf: controls whether noise will be eliminated from the signal input through the tc0in pin. when tc0nf = 0, the tc0in input is directly used as the tccap0 trigger input. when tc0nf = 1, high and low levels on tc0in shorter than 4/fsys (99 ns @fperiph = fc = 40.5 mhz) are regarded as noise and el iminated from the input. the elimination threshold varies with the clock gear setting. figure 13.5 tmrc registers cap0cr (0xffff_f413) note: bits 2 to 6 of the cap0cr are read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-269 tmrc capture 0 register (tccap0) 31 30 29 28 27 26 25 24 bit symbol cap031 cap030 cap029 cap028 cap027 cap026 cap025 cap024 read/write r reset value function capture 0 data 23 22 21 20 19 18 17 16 bit symbol cap023 cap022 cap021 cap020 cap019 cap018 cap017 cap016 read/write r reset value function capture 0 data 15 14 13 12 11 10 9 8 bit symbol cap015 cap014 cap013 cap012 cap011 cap010 cap09 cap08 read/write r reset value function capture 0 data 7 6 5 4 3 2 1 0 bit symbol cap07 cap06 cap05 cap04 cap03 cap02 cap01 cap00 read/write r reset value function capture 0 data tmrcg0 interrupt mask register 7 6 5 4 3 2 1 0 bit symbol tcim3 tcim2 tcim1 tcim0 read/write r/w reset value 0 0 0 0 function 1: masks intcap3. 1: masks intcap2. 1: masks intcap1. 1: masks intcap0. tmrcg0 status register 7 6 5 4 3 2 1 0 bit symbol intcap3 intcap2 intcap1 intcap0 read/write r reset value 0 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated figure 13.6 tmrc registers tccap0hh (0xffff_f414) tccap0hl (0xffff_f415) tccap0lh (0xffff_f416) tccap0ll (0xffff_f417) note 1: upon reset, the contents of the tccap0 are undefined. note 2: the counter value is not captured while the capture register is being read. tcg0im (0xffff_f40b) note: bits 4, 5, 6 and 7 of the tcg0im are read as 0. tcg0st (0xffff_f40a) note 1: reading the tcg0st register results in bits 0, 1, 2 and 3 being cleared. note 2: bits 4, 5, 6 and 7 of the tcg0st are read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-270 tmrc capture 1 control register 7 6 5 4 3 2 1 0 bit symbol tc1nf cp1eg1 cp1eg0 read/write r/w r/w reset value 0 0 0 function tc1in input noise elimination 0: not eliminated 1: eliminated tc1in edge detection 00: not captured 01: rising edge 10: falling edge 11: both edges cp1eg[1:0]: selects the edge to be detected on the tc1in pin for the tccap1. when cp1eg[1:0] = 00, capture is disabled for the tccap1. tc1nf: controls whether noise will be eliminated from the signal input through the tc1in pin. when tc1nf = 0, the tc1in input is directly used as the tccap1 trigger input. when tc1nf = 1, high and low levels on tc1in shorter than 4/fsys (99 ns @fperiph = fc = 40.5 mhz) are regarded as noise and el iminated from the input. the elimination threshold varies with the clock gear setting. tmrc capture 1 register (tccap1) 31 30 29 28 27 26 25 24 bit symbol cap131 cap130 cap129 cap128 cap127 cap126 cap125 cap124 read/write r reset value function capture 1 data 23 22 21 20 19 18 17 16 bit symbol cap123 cap122 cap121 cap120 cap119 cap118 cap117 cap116 read/write r reset value function capture 1 data 15 14 13 12 11 10 9 8 bit symbol cap115 cap114 cap113 cap112 cap111 cap110 cap19 cap18 read/write r reset value function capture 1 data 7 6 5 4 3 2 1 0 bit symbol cap17 cap16 cap15 cap14 cap13 cap12 cap11 cap10 read/write r reset value function capture 1 data figure 13.7 tmrc registers cap1cr (0xffff_f41b) note: bits 2 to 6 of the cap1cr are read as 0. tccap1hh (0xffff_f41c) tccap1hl (0xffff_f41d) tccap1lh (0xffff_f41e) tccap1ll (0xffff_f41f) note 1: upon reset, the contents of the tccap1 are undefined. note 2: the counter value is not captured while the capture register is being read. TMP1962C10BXBG 2006-02-21 tmp1962-271 tmrc capture 2 control register 7 6 5 4 3 2 1 0 bit symbol tc2nf cp2eg1 cp2eg0 read/write r/w r/w reset value 0 0 0 function tc2in input noise elimination 0: not eliminated 1: eliminated tc2in edge detection 00: not captured 01: rising edge 10: falling edge 11: both edges cp2eg[1:0]: selects the edge to be detected on the tc2in pin for the tccap2. when cp2eg[1:0] = 00, capture is disabled for the tccap2. tc2nf: controls whether noise will be eliminated from the signal input through the tc2in pin. when tc2nf = 0, the tc2in input is directly used as the tccap2 trigger input. when tc2nf = 1, high and low levels on tc2in shorter than 4/fsys (99 ns @fperiph = fc = 40.5 mhz) are regarded as noise and el iminated from the input. the elimination threshold varies with the clock gear setting. tmrc capture 2 register (tccap2) 31 30 29 28 27 26 25 24 bit symbol cap231 cap230 cap229 cap228 cap227 cap226 cap225 cap224 read/write r reset value function capture 2 data 23 22 21 20 19 18 17 16 bit symbol cap223 cap222 cap221 cap220 cap219 cap218 cap217 cap216 read/write r reset value function capture 2 data 15 14 13 12 11 10 9 8 bit symbol cap215 cap214 cap213 cap212 cap211 cap210 cap29 cap28 read/write r reset value function capture 2 data 7 6 5 4 3 2 1 0 bit symbol cap27 cap26 cap25 cap24 cap23 cap22 cap21 cap20 read/write r reset value function capture 2 data figure 13.8 tmrc registers cap2cr (0xffff_f423) note: bits 2 to 6 of the cap2cr are read as 0. tccap2hh (0xffff_f424) tccap2hl (0xffff_f425) tccap2lh (0xffff_f426) tccap2ll (0xffff_f427) note 1: upon reset, the contents of the tccap2 are undefined. note 2: the counter value is not captured while the capture register is being read. TMP1962C10BXBG 2006-02-21 tmp1962-272 tmrc capture 3 control register 7 6 5 4 3 2 1 0 bit symbol tc3nf cp3eg1 cp3eg0 read/write r/w r/w reset value 0 0 0 function tc3in input noise elimination 0: not eliminated 1: eliminated tc3in edge detection 00: not captured 01: rising edge 10: falling edge 11: both edges cp3eg[1:0]: selects the edge to be detected on the tc3in pin for the tccap3. when cp3eg[1:0] = 00, capture is disabled for the tccap3. tc3nf: controls whether noise will be eliminated from the signal input through the tc3in pin. when tc3nf = 0, the tc3in input is directly used as the tccap3 trigger input. when tc3nf = 1, high and low levels on tc3in shorter than 4/fsys (99 ns @fperiph = fc = 40.5 mhz) are regarded as noise and el iminated from the input. the elimination threshold varies with the clock gear setting. tmrc capture 3 register (tccap3) 31 30 29 28 27 26 25 24 bit symbol cap331 cap330 cap329 cap328 cap327 cap326 cap325 cap324 read/write r reset value function capture 3 data 23 22 21 20 19 18 17 16 bit symbol cap323 cap322 cap321 cap320 cap319 cap318 cap317 cap316 read/write r reset value function capture 3 data 15 14 13 12 11 10 9 8 bit symbol cap315 cap314 cap313 cap312 cap311 cap310 cap39 cap38 read/write r reset value function capture 3 data 7 6 5 4 3 2 1 0 bit symbol cap37 cap36 cap35 cap34 cap33 cap32 cap31 cap30 read/write r reset value function capture 3 data figure 13.9 tmrc registers cap3cr (0xffff_f42b) note: bits 2 to 6 of the cap3cr are read as 0. tccap3hh (0xffff_f42c) tccap3hl (0xffff_f42d) tccap3lh (0xffff_f42e) tccap3ll (0xffff_f42f) note 1: upon reset, the contents of the tccap3 are undefined. note 2: the counter value is not captured while the capture register is being read. TMP1962C10BXBG 2006-02-21 tmp1962-273 tmrc capture 4 control register 7 6 5 4 3 2 1 0 bit symbol tc4nf cp4eg1 cp4eg0 read/write r/w r/w reset value 0 0 0 function tc4in input noise elimination 0: not eliminated 1: eliminated tc4in edge detection 00: not captured 01: rising edge 10: falling edge 11: both edges cp4eg[1:0]: selects the edge to be detected on the tc4in pin for the tccap4. when cp4eg[1:0] = 00, capture is disabled for the tccap4. tc4nf: controls whether noise will be eliminated from the signal input through the tc4in pin. when tc4nf = 0, the tc4in input is directly used as the tccap4 trigger input. when tc4nf = 1, high and low levels on tc4in shorter than 4/fsys (99 ns @fperiph = fc = 40.5 mhz) are regarded as noise and el iminated from the input. the elimination threshold varies with the clock gear setting. tmrc capture 4 register (tccap4) 31 30 29 28 27 26 25 24 bit symbol cap431 cap430 cap429 cap428 cap427 cap426 cap425 cap424 read/write r reset value function capture 4 data 23 22 21 20 19 18 17 16 bit symbol cap423 cap422 cap421 cap420 cap419 cap418 cap417 cap416 read/write r reset value function capture 4 data 15 14 13 12 11 10 9 8 bit symbol cap415 cap414 cap413 cap412 cap411 cap410 cap49 cap48 read/write r reset value function capture 4 data 7 6 5 4 3 2 1 0 bit symbol cap47 cap46 cap45 cap44 cap43 cap42 cap41 cap40 read/write r reset value function capture 4 data figure 13.10 tmrc registers cap4cr (0xffff_f433) note: bits 2 to 6 of the cap4cr are read as 0. tccap4hh (0xffff_f434) tccap4hl (0xffff_f435) tccap4lh (0xffff_f436) tccap4ll (0xffff_f437) note 1: upon reset, the contents of the tccap4 are undefined. note 2: the counter value is not captured while the capture register is being read. TMP1962C10BXBG 2006-02-21 tmp1962-274 tmrcg1 interrupt mask register 7 6 5 4 3 2 1 0 bit symbol tbtim tcim7 tcim6 tcim5 tcim4 read/write r/w reset value 0 0 0 0 0 function 1: masks inttbt. 1: masks intcap7. 1: masks intcap6. 1: masks intcap5. 1: masks intcap4. tmrcg1 status register 7 6 5 4 3 2 1 0 bit symbol inttbt intcap7 intcap6 intcap5 intcap4 read/write r reset value 0 0 0 0 0 function 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated 0: no interrupt generated 1: interrupt generated figure 13.11 tmrc registers tcg1im (0xffff_f409) note: bits 5, 6 and 7 of the tcg1im are read as 0. tcg1st (0xffff_f408) note 1: reading the tcg1st register results in bits 0, 1, 2, 3 and 4 being cleared. note 2: bits 5, 6 and 7 of the tcg1st are read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-275 tmrc capture 5 control register 7 6 5 4 3 2 1 0 bit symbol tc5nf cp5eg1 cp5eg0 read/write r/w r/w reset value 0 0 0 function tc5in input noise elimination 0: not eliminated 1: eliminated tc5in edge detection 00: not captured 01: rising edge 10: falling edge 11: both edges cp5eg[1:0]: selects the edge to be detected on the tc5in pin for the tccap5. when cp5eg[1:0] = 00, capture is disabled for the tccap5. tc5nf: controls whether noise will be eliminated from the signal input through the tc5in pin. when tc5nf = 0, the tc5in input is directly used as the tccap5 trigger input. when tc5nf = 1, high and low levels on tc5in shorter than 4/fsys (99 ns @fperiph = fc = 40.5 mhz) are regarded as noise and el iminated from the input. the elimination threshold varies with the clock gear setting. tmrc capture 5 register (tccap5) 31 30 29 28 27 26 25 24 bit symbol cap531 cap530 cap529 cap528 cap527 cap526 cap525 cap524 read/write r reset value function capture 5 data 23 22 21 20 19 18 17 16 bit symbol cap523 cap522 cap521 cap520 cap519 cap518 cap517 cap516 read/write r reset value function capture 5 data 15 14 13 12 11 10 9 8 bit symbol cap515 cap514 cap513 cap512 cap511 cap510 cap59 cap58 read/write r reset value function capture 5 data 7 6 5 4 3 2 1 0 bit symbol cap57 cap56 cap55 cap54 cap53 cap52 cap51 cap50 read/write r reset value function capture 5 data figure 13.12 tmrc registers cap5cr (0xffff_f43b) note: bits 2 to 6 of the cap5cr are read as 0. tccap5hh (0xffff_f43c) tccap5hl (0xffff_f43d) tccap5lh (0xffff_f43e) tccap5ll (0xffff_f43f) note 1: upon reset, the contents of the tccap5 are undefined. note 2: the counter value is not captured while the capture register is being read. TMP1962C10BXBG 2006-02-21 tmp1962-276 tmrc capture 6 control register 7 6 5 4 3 2 1 0 bit symbol tc6nf cp6eg1 cp6eg0 read/write r/w r/w reset value 0 0 0 function tc6in input noise elimination 0: not eliminated 1: eliminated tc6in edge detection 00: not captured 01: rising edge 10: falling edge 11: both edges cp6eg[1:0]: selects the edge to be detected on the tc6in pin for the tccap6. when cp6eg[1:0] = 00, capture is disabled for the tccap6. tc6nf: controls whether noise will be eliminated from the signal input through the tc6in pin. when tc6nf = 0, the tc6in input is directly used as the tccap6 trigger input. when tc6nf = 1, high and low levels on tc6in shorter than 4/fsys (99 ns @fperiph = fc = 40.5 mhz) are regarded as noise and el iminated from the input. the elimination threshold varies with the clock gear setting. tmrc capture 6 register (tccap6) 31 30 29 28 27 26 25 24 bit symbol cap631 cap630 cap629 cap628 cap627 cap626 cap625 cap624 read/write r reset value function capture 6 data 23 22 21 20 19 18 17 16 bit symbol cap623 cap622 cap621 cap620 cap619 cap618 cap617 cap616 read/write r reset value function capture 6 data 15 14 13 12 11 10 9 8 bit symbol cap615 cap614 cap613 cap612 cap611 cap610 cap69 cap68 read/write r reset value function capture 6 data 7 6 5 4 3 2 1 0 bit symbol cap67 cap66 cap65 cap64 cap63 cap62 cap61 cap60 read/write r reset value function capture 6 data figure 13.13 tmrc registers cap6cr (0xffff_f443) note: bits 2 to 6 of the cap6cr are read as 0. tccap6hh (0xffff_f444) tccap6hl (0xffff_f445) tccap6lh (0xffff_f446) tccap6ll (0xffff_f447) note 1: upon reset, the contents of the tccap6 are undefined. note 2: the counter value is not captured while the capture register is being read. TMP1962C10BXBG 2006-02-21 tmp1962-277 tmrc capture 7 control register 7 6 5 4 3 2 1 0 bit symbol tc7nf cp7eg1 cp7eg0 read/write r/w r/w reset value 0 0 0 function tc7in input noise elimination 0: not eliminated 1: eliminated tc7in edge detection 00: not captured 01: rising edge 10: falling edge 11: both edges cp7eg[1:0]: selects the edge to be detected on the tc7in pin for the tccap7. when cp7eg[1:0] = 00, capture is disabled for the tccap7. tc7nf: controls whether noise will be eliminated from the signal input through the tc7in pin. when tc7nf = 0, the tc7in input is directly used as the tccap7 trigger input. when tc7nf = 1, high and low levels on tc7in shorter than 4/fsys (99 ns @fperiph = fc = 40.5 mhz) are regarded as noise and el iminated from the input. the elimination threshold varies with the clock gear setting. tmrc capture 7 register (tccap7) 31 30 29 28 27 26 25 24 bit symbol cap731 cap730 cap729 cap728 cap727 cap726 cap725 cap724 read/write r reset value function capture 7 data 23 22 21 20 19 18 17 16 bit symbol cap723 cap722 cap721 cap720 cap719 cap718 cap717 cap716 read/write r reset value function capture 7 data 15 14 13 12 11 10 9 8 bit symbol cap715 cap714 cap713 cap712 cap711 cap710 cap79 cap78 read/write r reset value function capture 7 data 7 6 5 4 3 2 1 0 bit symbol cap77 cap76 cap75 cap74 cap73 cap72 cap71 cap70 read/write r reset value function capture 7 data figure 13.14 tmrc registers cap7cr (0xffff_f44b) note: bits 2 to 6 of the cap7cr are read as 0. tccap7hh (0xffff_f44c) tccap7hl (0xffff_f44d) tccap7lh (0xffff_f44e) tccap7ll (0xffff_f44f) note 1: upon reset, the contents of the tccap7 are undefined. note 2: the counter value is not captured while the capture register is being read. TMP1962C10BXBG 2006-02-21 tmp1962-278 tmrc compare control register (cmpctl) 31 30 29 28 27 26 25 24 bit symbol tcffen7 tcffc71 tcffc70 cmprde7 cmpen7 read/write r/w w r/w reset value 0 0 1 1 0 0 0 0 function tcff7 toggle trigger 0: disable 1: enable tcff7 control 00: toggle 01: set 10: clear 11: don't care double-bu ffering 7 0: disable 1: enable compare 7 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol tcffen6 tcffc61 tcffc60 cmprde6 cmpen6 read/write r/w w r/w reset value 0 0 1 1 0 0 0 0 function tcff6 toggle trigger 0: disable 1: enable tcff6 control 00: toggle 01: set 10: clear 11: don't care double-bu ffering 6 0: disable 1: enable compare 6 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol tcffen5 tcffc51 tcffc50 cmprde5 cmpen5 read/write r/w w r/w reset value 0 0 1 1 0 0 0 0 function tcff5 toggle trigger 0: disable 1: enable tcff5 control 00: toggle 01: set 10: clear 11: don't care double-bu ffering 5 0: disable 1: enable compare 5 0: disable 1: enable 7 6 5 4 3 2 1 0 bit symbol tcffen4 tcffc41 tcffc40 cmprde4 cmpen4 read/write r/w w r/w reset value 0 0 1 1 0 0 0 0 function tcff4 toggle trigger 0: disable 1: enable tcff4 control 00: toggle 01: set 10: clear 11: don't care double-bu ffering 4 0: disable 1: enable compare 4 0: disable 1: enable cmpctl7 (0xffff_f474) cmpctl6 (0xffff_f475) cmpctl5 (0xffff_f476) cmpctl4 (0xffff_f477) TMP1962C10BXBG 2006-02-21 tmp1962-279 tmrc compare control register (cmpctl) 31 30 29 28 27 26 25 24 bit symbol tcffen3 tcffc31 tcffc30 cmprde3 cmpen3 read/write r/w w r/w reset value 0 0 1 1 0 0 0 0 function tcff3 toggle trigger 0: disable 1: enable tcff3 control 00: toggle 01: set 10: clear 11: don't care double-bu ffering 3 0: disable 1: enable compare 3 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol tcffen2 tcffc21 tcffc20 cmprde2 cmpen2 read/write r/w w r/w reset value 0 0 1 1 0 0 0 0 function tcff2 toggle trigger 0: disable 1: enable tcff2 control 00: toggle 01: set 10: clear 11: don't care double-bu ffering 2 0: disable 1: enable compare 2 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol tcffen1 tcffc11 tcffc10 cmprde1 cmpen1 read/write r/w w r/w reset value 0 0 1 1 0 0 0 0 function tcff1 toggle trigger 0: disable 1: enable tcff1 control 00: toggle 01: set 10: clear 11: don't care double-bu ffering 1 0: disable 1: enable compare 1 0: disable 1: enable 7 6 5 4 3 2 1 0 bit symbol tcffen0 tcffc01 tcffc00 cmprde0 cmpen0 read/write r/w w r/w reset value 0 0 1 1 0 0 0 0 function tcff0 toggle trigger 0: disable 1: enable tcff0 control 00: toggle 01: set 10: clear 11: don't care double-bu ffering 0 0: disable 1: enable compare 0 0: disable 1: enable cmpenn: enables or disables the de tection of a match in comparison. cmprden: enables or disables double-buffering for the compare register. tcffcn[1:0]: controls the compare match output flip-flop. tcffenn: enables or disables the toggling of the compare match output flip-flop. figure 13.15 tmrc registers cmpctl3 (0xffff_f470) cmpctl2 (0xffff_f471) cmpctl1 (0xffff_f472) cmpctl0 (0xffff_f473) note: bits 31, 27, 26, 23, 19, 18, 15, 11, 10, 7, 3 and 2 of the cmptcl are read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-280 tmrc compare register 0 (tccmp0) 31 30 29 28 27 26 25 24 bit symbol cmp031 cmp030 cmp029 cmp028 cmp027 cmp026 cmp025 cmp024 read/write w reset value function compare register 0 data 23 22 21 20 19 18 17 16 bit symbol cmp023 cmp022 cmp021 cmp020 cmp019 cmp018 cmp017 cmp016 read/write w reset value function compare register 0 data 15 14 13 12 11 10 9 8 bit symbol cmp015 cmp014 cmp013 cmp012 cmp011 cmp010 cmp09 cmp08 read/write w reset value function compare register 0 data 7 6 5 4 3 2 1 0 bit symbol cmp07 cmp06 cmp05 cmp04 cmp03 cmp02 cmp01 cmp00 read/write w reset value function compare register 0 data tmrc compare register 1 (tccmp1) 31 30 29 28 27 26 25 24 bit symbol cmp131 cmp130 cmp129 cmp128 cmp127 cmp126 cmp125 cmp124 read/write w reset value function compare register 1 data 23 22 21 20 19 18 17 16 bit symbol cmp123 cmp122 cmp121 cmp120 cmp119 cmp118 cmp117 cmp116 read/write w reset value function compare register 1 data 15 14 13 12 11 10 9 8 bit symbol cmp115 cmp114 cmp113 cmp112 cmp111 cmp110 cmp19 cmp18 read/write w reset value function compare register 1 data 7 6 5 4 3 2 1 0 bit symbol cmp17 cmp16 cmp15 cmp14 cmp13 cmp12 cmp11 cmp10 read/write w reset value function compare register 1 data figure 13.16 tmrc registers tccmp0hh (0xffff_f450) tccmp0hl (0xffff_f451) tccmp0lh (0xffff_f452) tccmp0ll (0xffff_f453) note: the tccmp0 is a write-only register. upon reset, its contents are undefined. tccmp1hh (0xffff_f454) tccmp1hl (0xffff_f455) tccmp1lh (0xffff_f456) tccmp1ll (0xffff_f457) note: the tccmp1 is a write-only register. upon reset, its contents are undefined. TMP1962C10BXBG 2006-02-21 tmp1962-281 tmrc compare register 2 (tccmp2) 31 30 29 28 27 26 25 24 bit symbol cmp231 cmp230 cmp229 cmp228 cmp227 cmp226 cmp225 cmp224 read/write w reset value function compare register 2 data 23 22 21 20 19 18 17 16 bit symbol cmp223 cmp222 cmp221 cmp220 cmp219 cmp218 cmp217 cmp216 read/write w reset value function compare register 2 data 15 14 13 12 11 10 9 8 bit symbol cmp215 cmp214 cmp213 cmp212 cmp211 cmp210 cmp29 cmp28 read/write w reset value function compare register 2 data 7 6 5 4 3 2 1 0 bit symbol cmp27 cmp26 cmp25 cmp24 cmp23 cmp22 cmp21 cmp20 read/write w reset value function compare register 2 data tmrc compare register 3 (tccmp3) 31 30 29 28 27 26 25 24 bit symbol cmp331 cmp330 cmp329 cmp328 cmp327 cmp326 cmp325 cmp324 read/write w reset value function compare register 3 data 23 22 21 20 19 18 17 16 bit symbol cmp323 cmp322 cmp321 cmp320 cmp319 cmp318 cmp317 cmp316 read/write w reset value function compare register 3 data 15 14 13 12 11 10 9 8 bit symbol cmp315 cmp314 cmp313 cmp312 cmp311 cmp310 cmp39 cmp38 read/write w reset value function compare register 3 data 7 6 5 4 3 2 1 0 bit symbol cmp37 cmp36 cmp35 cmp34 cmp33 cmp32 cmp31 cmp30 read/write w reset value function compare register 3 data figure 13.17 tmrc registers tccmp2hh (0xffff_f458) tccmp2hl (0xffff_f459) tccmp2lh (0xffff_f45a) tccmp2ll (0xffff_f45b) note: the tccmp2 is a write-only register. upon reset, its contents are undefined. tccmp3hh (0xffff_f45c) tccmp3hl (0xffff_f45d) tccmp3lh (0xffff_f45e) tccmp3ll (0xffff_f45f) note: the tccmp3 is a write-only register. upon reset, its contents are undefined. TMP1962C10BXBG 2006-02-21 tmp1962-282 tmrc compare register 4 (tccmp4) 31 30 29 28 27 26 25 24 bit symbol cmp431 cmp430 cmp429 cmp428 cmp427 cmp426 cmp425 cmp424 read/write w reset value function compare register 4 data 23 22 21 20 19 18 17 16 bit symbol cmp423 cmp422 cmp421 cmp420 cmp419 cmp418 cmp417 cmp416 read/write w reset value function compare register 4 data 15 14 13 12 11 10 9 8 bit symbol cmp415 cmp414 cmp413 cmp412 cmp411 cmp410 cmp49 cmp48 read/write w reset value function compare register 4 data 7 6 5 4 3 2 1 0 bit symbol cmp47 cmp46 cmp45 cmp44 cmp43 cmp42 cmp41 cmp40 read/write w reset value function compare register 4 data tmrc compare register 5 (tccmp5) 31 30 29 28 27 26 25 24 bit symbol cmp531 cmp530 cmp529 cmp528 cmp527 cmp526 cmp525 cmp524 read/write w reset value function compare register 5 data 23 22 21 20 19 18 17 16 bit symbol cmp523 cmp522 cmp521 cmp520 cmp519 cmp518 cmp517 cmp516 read/write w reset value function compare register 5 data 15 14 13 12 11 10 9 8 bit symbol cmp515 cmp514 cmp513 cmp512 cmp511 cmp510 cmp59 cmp58 read/write w reset value function compare register 5 data 7 6 5 4 3 2 1 0 bit symbol cmp57 cmp56 cmp55 cmp54 cmp53 cmp52 cmp51 cmp50 read/write w reset value function compare register 5 data figure 13.18 tmrc registers tccmp4hh (0xffff_f460) tccmp4hl (0xffff_f461) tccmp4lh (0xffff_f462) tccmp4ll (0xffff_f463) note: the tccmp4 is a write-only register. upon reset, its contents are undefined. tccmp5hh (0xffff_f464) tccmp5hl (0xffff_f465) tccmp5lh (0xffff_f466) tccmp5ll (0xffff_f467) note: the tccmp5 is a write-only register. upon reset, its contents are undefined. TMP1962C10BXBG 2006-02-21 tmp1962-283 tmrc compare register 6 (tccmp6) 31 30 29 28 27 26 25 24 bit symbol cmp631 cmp630 cmp629 cmp628 cmp627 cmp626 cmp625 cmp624 read/write w reset value function compare register 6 data 23 22 21 20 19 18 17 16 bit symbol cmp623 cmp622 cmp621 cmp620 cmp619 cmp618 cmp617 cmp616 read/write w reset value function compare register 6 data 15 14 13 12 11 10 9 8 bit symbol cmp615 cmp614 cmp613 cmp612 cmp611 cmp610 cmp69 cmp68 read/write w reset value function compare register 6 data 7 6 5 4 3 2 1 0 bit symbol cmp67 cmp66 cmp65 cmp64 cmp63 cmp62 cmp61 cmp60 read/write w reset value function compare register 6 data tmrc compare register 7 (tccmp7) 31 30 29 28 27 26 25 24 bit symbol cmp731 cmp730 cmp729 cmp728 cmp727 cmp726 cmp725 cmp724 read/write w reset value function compare register 7 data 23 22 21 20 19 18 17 16 bit symbol cmp723 cmp722 cmp721 cmp720 cmp719 cmp718 cmp717 cmp716 read/write w reset value function compare register 7 data 15 14 13 12 11 10 9 8 bit symbol cmp715 cmp714 cmp713 cmp712 cmp711 cmp710 cmp79 cmp78 read/write w reset value function compare register 7 data 7 6 5 4 3 2 1 0 bit symbol cm77 cmp76 cmp75 cmp74 cmp73 cmp72 cmp71 cmp70 read/write w reset value function compare register 7 data figure 13.19 tmrc registers tccmp6hh (0xffff_f468) tccmp6hl (0xffff_f469) tccmp6lh (0xffff_f46a) tccmp6ll (0xffff_f46b) note: the tccmp6 is a write-only register. upon reset, its contents are undefined. tccmp7hh (0xffff_f46c) tccmp7hl (0xffff_f46d) tccmp7lh (0xffff_f46e) tccmp7ll (0xffff_f46f) note: the tccmp7 is a write-only register. upon reset, its contents are undefined. TMP1962C10BXBG 2006-02-21 tmp1962-284 14. serial i/o (sio) the tmp1962 serial i/o contains seven channels (sio0-sio6). each serial channel provides universal asynchronous receiver/transmitter (uart) mode and synchronous i/o interface mode. ? i/o interface mode mode 0: transmits/receives a seri al clock (sclk) as well as data streams for a synchronous clock mode of operation. mode 1: 7 data bits ? uart mode mode 2: 8 data bits mode 3: 9 data bits in mode 1 and mode 2, each frame can include a parity bit. in mode 3, an sio channel operates in a wakeup mode for multidrop applications in which a master station is connected to several slave stations through a serial link. figure 14.2 shows a block diagram of the sio0. the main components of an sio channel are a clock prescaler, a seri al clock generator, a receive buffer, a receive controller, a transmit buffer and a transmit contro ller. each sio channel is independently programmable, and functionally equivalent. in the following sections, any re ferences to the sio0 also apply to the other channels. bit 0 123456 start stop bit 0 123456 start stop parity bit 0 123456 bit 0 123456 start stop start stop parity 77 7 bit 0 123456 start 87 stop bit 0 123456 start stop (wake-up) bit 8 7 bit 8: address/data bit flag 1: address frame (select code) 0: data frame ? mode 0 (i/o interface mode): msb first goes out first ? mode 1 (7-bit uart mode) ? mode 2 (8-bit uart mode) ? mode 3 (9-bit uart mode) without parity with parity without parity with parity 0 bit 7 654321 ? mode 0 (i/o interface mode): lsb first goes out first 7 bit 0 123456 figure 14.1 data formats TMP1962C10BXBG 2006-02-21 tmp1962-285 14.1 block diagram (channel 0) figure 14.2 sio block diagram sc0mod0 TMP1962C10BXBG 2006-02-21 tmp1962-286 14.2 sio components (channel 0) 14.2.1 prescaler the sio0 has a 6-bit prescaler that slows the rate of a clocking source to the serial clock generator. the prescaler clock source ( t0) can be selected from fperiph/4, fperiph/8 and fperiph/16 by programming the prck[1:0] field of the syscr located within th e cg. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming th e fpsel bit of the syscr1 located within the cg. the serial clock is selectable fr om several clocks; the prescaler is only enabled when the baud rate generator output clock is selected as a serial clock. table 14.1 shows prescaler output clock resolutions. table 14.1 prescaler output clock resolutions @ = 40.5 mhz prescaler output clock resolution peripheral clock select fpsel clock gear value gear[1:0] prescaler clock source prck[1:0] t0 t2 t8 t32 00 (fperiph/16) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) fc/2 10 (25.3 s) 01 (fperiph/8) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.6 s) 00 (fc) 10 (fperiph/4) fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) 00 (fperiph/16) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.6 s) fc/2 11 (50.6 s) 01 (fperiph/8) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) fc/2 10 (25.3 s) 01 (fc/2) 10 (fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.6 s) 00 (fperiph/16) fc/2 6 (1.6 s) fc/2 8 (6.3 s) fc/2 10 (25.3 s) fc/2 12 (101 s) 01 (fperiph/8) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.6 s) fc/2 11 (50.6 s) 10 (fc/4) 10 (fperiph/4) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) fc/2 10 (25.3 s) 00 (fperiph/16) fc/2 7 (3.2 s) fc/2 9 (12.6 s) fc/2 11 (50.6 s) fc/2 13 (202 s) 01 (fperiph/8) fc/2 6 (1.6 s) fc/2 8 (6.3 s) fc/2 10 (25.3 s) fc/2 12 (101 s) 0 (fgear) 11 (fc/8) 10 (fperiph/4) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.6 s) fc/2 11 (50.6 s) 00 (fperiph/16) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) fc/2 10 (25.3 s) 01 (fperiph/8) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.6 s) 00 (fc) 10 (fperiph/4) fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) 00 (fperiph/16) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) fc/2 10 (25.3 s) 01 (fperiph/8) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.6 s) 01 (fc/2) 10 (fperiph/4) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) 00 (fperiph/16) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) fc/2 10 (25.3 s) 01 (fperiph/8) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.6 s) 10 (fc/4) 10 (fperiph/4) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.3 s) 00 (fperiph/16) ? fc/2 6 (1.6 s) fc/2 8 (6.3 s) fc/2 10 (25.3 s) 01 (fperiph/8) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.6 s) 1 (fc) 11 (fc/8) 10 (fperiph/4) ? ? fc/2 6 (1.6 s) fc/2 8 (6.3 s) prescaler output taps can be divide-by-1 ( t0), divide-by-4 ( t2), divide-by-16 ( t8) and divide-by-64 ( t32). note 1: the prescaler's output clock tn must be selected so that the relationship tn < fsys/2 is satisfied. note 2: do not change the clock gear value while the sio0 is operating. note 3: the - character means "setting prohibited. TMP1962C10BXBG 2006-02-21 tmp1962-287 14.2.2 baud rate generator the frequency used to transmit and receive data through the sio0 is derived from the baud rate generator. the clock source for the baud rate generato r can be selected from th e 6-bit prescaler outputs ( t0, t2, t8, t32) through the programming of the br0ck[1:0] field in the br0cr. the baud rate generator contains a clock divider that can divide the selected clock by 1, n + (m/16), or 16 (where n is an integer between 2 and 15, and m is an integer between 0 and 15). the clock divisor is programmed into the br0adde and br0s[3:0] bits in the br0cr and the br0k[3:0] bits in the br0add. ? uart mode (1) when br0cr.br0adde = 0 when the br0cr.br0adde bit is cleared, the br0add .br0k[3:0] field has no meaning or effect. in this case, the baud rate generator input clock is divided down by a value of n (1 to 16) programmed in the br0cr.br0s[3:0] field. (2) when br0cr.br0adde = 1 setting the br0cr.br0adde bit enables the n + (16 - k)/16 clock division function. the baud rate generator input clock is divided down according to the value of n (2 to 15) programmed in the br0cr.br0s[3:0] field and the value of k (1 to 15) programmed in the br0add.br0k[3:0] field. ? i/o interface mode i/o interface mode cannot utilize the n + (16 - k)/16 clock division function. the br0cr.br0adde must be cleared, so the baud rate generator input clock is divided down by a value of n (1 to 16) programmed in the br0cr.br0s[3:0] field. ? baud rate calculations (1) uart mode baud rate = baud rate generator input clock / baud rate generator divisor 16 when the clock input to the baud rate generator is 10.125-mhz t0, the maximum baud rate is 632.8 kbps. the baud rate generator can be bypassed if the user wants to use the fsys/2 clock as a serial clock. in this case, the maximum baud rate is 1.266 mbps @fsys = 40.5 mhz. note: setting n to 1 or 16 disables the n + (16 - k)/16 clock division function. when n = 1 or 16, the br0cr.br0adde bit must be cleared. TMP1962C10BXBG 2006-02-21 tmp1962-288 (2) i/o interface mode baud rate = baud rate generator input clock / baud rate generator divisor 2 when the clock input to the baud rate generator is 10.125-mhz t0, the maximum baud rate is 5.06 mbps (with no clock division by the baud rate generator) if double-buffering is used, or 2.53 mbps (with the clock divided by 2 by the baud rate generator) if double-buffering is not used. ? calculation examples (1) integral clock division (divide-by-n) fperiph = 40.5-mhz fc t0 = fperiph/16 baud rate generator input clock: t2 clock divisor n (br0cr.br0s[3:0]) = 4 br0cr.br0adde = 0 clocking conditions system clock: high-speed (fc) high-speed clock gear: x1 (fc) prescaler clock: f periph /16 (f periph = f sys ) the baud rate in uart mode is determined as follows: baud rate = (fc/64)/4 16 = 40.5 x 10 6 64 4 16 = 9888 (bps) (2) n + (16 - k)/16 clock division (uart mode only) fperiph = 19.2-mhz fc t0 = fperiph/16 baud rate generator input clock: t2 n (br0cr.br0s[3:0]) = 4 k (br0add.br0k[3:0]) = 14 br0cr.br0adde = 1 clocking conditions system clock: high-speed (fc) high-speed clock gear: x1 (fc) prescaler clock: f periph /4 (f periph = f sys ) the baud rate is determined as follows: baud rate = (fc/64)/(4 + (16-14)/16) 16 = 40.5 x 10 6 64 (4 + 2/16) 16 = 9588 (bps) note: clearing the br0cr.br0adde bit to 0 disables the n + (16 - k)/16 clock division function. at this time, the br0add.br0k[3:0] field is ignored. TMP1962C10BXBG 2006-02-21 tmp1962-289 the sio0 can use an external clock as a serial clock, bypassing the baud rate generator. when an external clock is used, the baud rate is determined as shown below. ? using an external clock as a serial clock (1) uart mode baud rate = external clock input 16 the external clock period must be greater than or equal to 4/fsys. therefore, when fsys =40.5 mhz, the maximum baud rate is 632.8 kbps (40.5 4 16). (2) i/o interface mode baud rate = external clock input clock when double-buffering is used, the external clock period must be greater than 12/fsys. therefore, when fsys = 40.5 mhz, the maximum baud rate is 3.375 mbps (40.5 12). when double-buffering is not used, the external clock period must be greater than 16/fsys. therefore, when fsys = 40.5 mhz, the maximum baud rate is 2.53 mbps (40.5 16). table 14.2 and table 14.3 show the uart baud rates obtained with various combinations of clock inputs and clock divisor values. TMP1962C10BXBG 2006-02-21 tmp1962-290 table 14.2 uart baud rate selection (when the baud rate generator is used and br0cr.br0adde = 0) unit: kbps fc [mhz] baud rate generator input clock divisor n (programmed in br0cr.br0s[3:0]) t0 (fc/4) t2 (fc/16) t8 (fc/64) t32 (fc/256) 19.6608 1 307.200 76.800 19.200 4.800 2 153.600 38.400 9.600 2.400 4 76.800 19.200 4.800 1.200 8 38.400 9.600 2.400 0.600 0 19.200 4.800 1.200 0.300 24.576 5 76.800 19.200 4.800 1.200 a 38.400 9.600 2.400 0.600 29.4912 1 460.800 115.200 28.800 7.200 2 230.400 57.600 14.400 3.600 3 153.600 38.400 9.600 2.400 4 115.200 28.800 7.200 1.800 6 76.800 19.200 4.800 1.200 c 38.400 9.600 2.400 0.600 table 14.3 uart baud rate selection (when the tmrab timer trigger output (internal ta bout) is used and the tmrab input clock is t1) unit: kbps fc ta0reg 29.4912 mhz 24.576 mhz 24 mhz 19.6608 mhz 16 mhz 12.288 mhz 1h 230.4 192 187.5 153.6 125 96 2h 115.2 96 93.75 76.8 62.5 48 3h 76.8 64 62.5 51.2 41.67 32 4h 57.6 48 46.88 38.4 31.25 24 5h 46.08 38.4 37.5 30.72 25 19.2 6h 38.4 32 31.25 25.6 20.83 16 8h 28.8 24 23.44 19.2 15.63 12 ah 23.04 19.2 18.75 15.36 12.5 9.6 10h 14.4 12 11.72 9.6 7.81 6 14h 11.52 9.6 9.38 7.68 6.25 4.8 when the 8-bit timer tmrab is used to generate a serial clock, the baud rate is determined by the following equation: baud rate = clock frequency selected by syscr0.prck[1:0] tabreg 2 16 when the tmrab clock source is t1 note: this table assumes: fsys = fc, clock gear = fc/1, prescaler clock source = f periph /4 note 1: i/o interface mode cannot utilize the trigger outp ut signal (internal) from the 8-bit timer tmrab as a serial clock. note 2: this table assumes: fsys = fc, clock gear = fc/1, prescaler clock source = fperiph/4 TMP1962C10BXBG 2006-02-21 tmp1962-291 14.2.3 serial clock generator this block generates a basic clock that co ntrols the transmit and receive circuit. ? i/o interface mode if the sclk0 pin is configured as an output by clearing the sc0cr.ioc bit to 0, the output clock from the baud rate generator is divided by two to generate the basic clock. if the sclk0 pin is configured as an input by setting the sc0cr.ioc bit to 1, the external sclk0 clock is used as the basic clock; the sc0cr.sclks bit determines the active clock edge. ? uart mode the basic clock (sioclk) is selected from a clock produced by the baud rate generator, the system clock (f sys /2), the internal output signal from the 8-bit timer tmrab, and the external sclk0 clock, according to the setti ng of the sc0mod0. sc[1:0] field. 14.2.4 receive counter the receive counter is a 4-bit binary up-counter used in uart mode. this counter is clocked by sioclk. the receiver utilizes 16 cl ocks for each received bit, and oversamples each bit three times around their center (with 7th to 9th clocks). the value of a bit is determined by voting logic which takes the value of the majority of three samples. 14.2.5 receive controller ? i/o interface mode if the sclk0 pin is configured as an output by clearing the sc0cr.ioc bit to 0, the receive controller samples the rxd0 input at the rising edge of the shift clock driven out from the sclk0 pin. if the sclk0 pin is configured as an input by setting the sc0cr.ioc bit to 1, the receive controller samples the rxd0 input at either the rising or falling edge of the sclk0 clock, as programmed in the sc0cr.sclks bit. ? uart mode the receive controller contains the start bit detecti on logic. once a valid start bit is detected, the receive controller begins samp ling the incoming data streams. 14.2.6 receive buffer the receive buffer is double-buffered to prevent overrun errors. received data is serially shifted bit by bit into receive buffer 1. when a wh ole frame is loaded into receive buff er 1, it is transferred to receive buffer 2 (sc0buf), and a receive-done interrupt (intrx0) is generated. at this time, the receive buffer full flag (sc0mod2.rbfll) is set to 1, indicatin g that receive buffer 2 contains valid data. the cpu reads a frame from receive buffer 2 (s c0buf), causing the recei ve buffer full flag (sc0mod2.rbfll) to be cleared to 0. receive buff er 1 can accept a new frame through the rxd0 pin before the cpu picks up the previous frame in receive buffer 2. TMP1962C10BXBG 2006-02-21 tmp1962-292 if the sclk0 pin is configured as an output in i/ o interface mode, receive buffer 2 (sc0buf) can be enabled or disabled by programming the wbuf b it in the sc0mod2. disabling receive buffer 2 (double-buffering) enables handshaking during data transfer; the sio0 stops outputting the sclk0 clock every time a single frame has transm itted. in this case, the cpu read s a frame from receive buffer 1, causing the output of the sclk0 clock to be restarted. if receive buffer 2 (doubl e-buffering) is enabled, a received frame is transferred from receive buffer 1 to receive buffer 2. once a next frame is received, resulting in both receive buffers 1 and 2 containing valid data, the sio0 stops outputting the sclk0 clock. when the cpu reads a frame from receive buffer 2, the frame stored in receive buffer 1 is transferred to receive buffer 2, causing a receive-done interrupt (intrx0) to occur and the sio0 to restart outputting the sclk0 clock. consequently, no overrun error occurs if the sclk0 pin is configured as an output in i/o interface mode, regardless of the setting of the sc0mod2.wbuf bit. in other operating modes, receive buffer 2 is always enabled to improve performance during continuous transfer. however, the cpu must read recei ve buffer 2 before receive buffer 1 is filled with a new frame. otherwise, an overrun error occurs, causi ng the frame previously in receive buffer 1 to be lost. even in that case, the contents of receive buffer 2 and the sc0cr. rb8 bit are preserved. the sc0cr.rb8 bit holds the parity bit for an 8-bit uart frame and the most significant bit for a 9-bit uart frame. in 9-bit uart mode, the receiver wake-up feature allows the slave station in a multidrop system to wake up whenever an address frame is received. setting the sc0mod0.wu bit enables the wake-up feature. the receiver generates the intrx0 interrupt only when the sc0cr.rb8 bit is set to 1. 14.2.7 transmit counter the transmit counter is a 4-bit binary up-counter used in uart mode. like the receive counter, the transmit counter is also clocked by sioclk. the transmitter generates a transmit clock (txdclk) pulse every 16 sioclk pulses. figure 14.3 transmit clock generation 14.2.8 transmit controller ? i/o interface mode if the sclk0 pin is configured as an output by clearing the sc0cr.ioc bit to 0, the transmit controller shifts out each bit in the transmit buffer to the txd0 pin at the rising edge of the shift clock driven out on the sclk0 pin. if the sclk0 pin is configured as an input by setting the sc0cr.ioc bit to 1, the transmit controller shif ts out each bit in the transmit buffer to the txd0 pin at either the rising or falling edge of the sclk0 input, as programmed in the sc0cr.sclks bit. note: in this mode, the oeer flag in the sc0cr has no meaning; it is read as undefined. when exiting sclk output mode, first read the sc0cr to initialize this flag. sioclk txdclk 15 16 1 2 4 5 67 8 910 11 12 13 14 15 16 3 1 2 TMP1962C10BXBG 2006-02-21 tmp1962-293 ? uart mode once the cpu loads a frame into the transmit bu ffer, the transmit controller begins transmission at the next rising edge of txdclk, producing a transmit shift clock (txdsft). handshaking the sio0 has the clear-to-send (cts) pin. if th e cts operation is enabled, the cts input must be low in order for the frame to be transmitted. this feature can be used for flow control to prevent overrun in the receiver. the sc0m od.ctse bit enables and disables the cts operation. if the cts pin goes high in the middle of a transmission, the transmit controller stops transmission upon completion of the current frame until cts again goes low. if so enabled, the transmit controller generates the inttx0 interrupt to notify the cpu that the transmit buffer is empty. after the cpu loads the next frame into the transmit buffer, the transmit controller remains in idle state until it detects cts going low. although the sio0 does not have an rts pin, any general-purpose port pin can serve as the rts pin. the receiving device uses the rts output to control the cts input of the transmitting device. once the receiving device has received a frame, rts should be set to high in the receive-done interrupt handler to temporarily stop the transmitting device from sending the next frame. this way, the user can easily im plement a two-way handshake protocol. figure 14.4 handshaking signals figure 14.5 clear-to-send ( cts ) signal timing rxd rts (any port) receiving device transmitting device txd cts tmp1962 tmp1962 note: (1) when cts goes high in the middle of transmission, the transmitter stops transmission after the current frame has been sent. (2) the transmitter starts transmission at the first falling edge of the txdclk clock after the cts signal goes low. cts (1) (2) 13 14 15 16 1 2 3 14 15 16 1 2 3 sioclk txdclk txd bit 0 start bit no transmission takes place during this period. write to the transmit buffer TMP1962C10BXBG 2006-02-21 tmp1962-294 14.2.9 transmit buffer the transmit buffer is double-buffered. double-buffering can be enabled or disabled by programming the wbuf bit in the sc0mod2. if double-buffering is enabled, a frame is first written to transmit buffer 2 (sc0buf) and then transferred to transmit buffer 1 (shift register), causing the inttx interrupt to occur and the transfer buffer empty flag (sc0mod2.tbemp) to be set. th is flag indicates that transfer buffer 2 is empty and a next transmit frame can be written. writing a next frame to transmit buffer 2 clears the tbemp flag. when the sclk0 pin is configured as an input in i/o interface mode, an un derrun error occurs upon the completion of transmitting a frame from transmit buffer 1, if a next frame is not written to transfer buffer 2 before the clock pulse for the next frame is input. an underrun error is indicated by the parity/underrun flag (perr) in the sc0cr. when the sclk0 pin is configured as an output in i/o interface mode, the sio0 stops outputting the sclk 0 clock after transmitting a frame which has been transferred from transmit buffer 2 to transmit buff er 1. in this mode, therefore, no underrun error occurs. if double-buffering is disabled, the cpu writes a transmit frame to transmit buffer 1. the inttx interrupt is generated upon the completion of transmission. if handshaking is required, transmit buffer 2 must be disabled by clearing the wbuf bit in the sc0mod2. for continuous transmission without handshaking, transmit buffer 2 can be enabled, by setting the wbuf bit, to improve performance. 14.2.10 parity controller for transmit operations, setting the sc0cr.pe bit enables parity generation in 7- and 8-bit uart modes. the sc0cr.even bit select s either even or odd parity. if enabled, the parity controller automatically ge nerates parity for the frame in the transmit buffer (sc0buf). in 7-bit uart mode, the tb7 bit in the sc0buf holds the parity bit. in 8-bit uart mode, the tb8 bit in the sc0mod holds the parity bit. the pa rity bit is set after the frame has been transmitted. the sc0cr.pe and sc0cr.even bits must be prog rammed prior to a write to the transmit buffer. for receive operations, the parity controller automatic ally computes the expected parity when a frame in receive buffer 1 is transferred to receive buffer 2 (sc0buf). the received parity bit is compared to the sc0buf.rb7 bit in 7-bit uart mode and to the sc0cr.rb8 bit in 8-bit uart mode. if a frame is received with incorrect parity , the sc0cr.perr bit is set. in i/o interface mode, the sc0cr.perr bit indicates an underrun error rather than a parity error. note: when the sclk0 pin is configured as an output in i/o interface mode, the peer flag in the sc0cr has no meaning; it is read as undefined. when exiting sclk ou tput mode, first read the sc0cr to initialize this flag. TMP1962C10BXBG 2006-02-21 tmp1962-295 14.2.11 error flags the sio0 has the following error flag bits that i ndicate the status of the received frame for improved data reception reliability. (1) overrun error (oerr): bit 4 of the sc0cr in uart and i/o interface modes, an overrun error is reported with the oerr b it set to 1 if all bits of a new frame are received before the cpu reads the current frame from the receive buffer. reading the flag causes it to be cleared. when the sclk0 pin is configured as an output in i/o interface mode, however, no overrun error occurs so that the oeer flag has no meaning and is read as undefined. (2) parity error/underrun error (perr): bit 3 of the sc0cr in uart mode, this flag indicates whether a parity error has occurred. a parity error is reported when the parity bit att ached to a received frame does not match the expected parity computed from the frame. reading the flag causes it to be cleared. in i/o interface mode, this flag indicates whether an underrun error has occurred, only when double-buffering (transmit buffer 2) is en abled (sc0mod2.wbuf = 1) with the sclk0 pin configured as an input. an underrun error is reported upon the completion of transmitting a frame from transmit buffer 1, if a next frame is not wr itten to transfer buffer 2 before the clock pulse for the next frame is input. when the sclk0 pin is configured as an output, no underrun error occurs so that the peer flag has no meaning and is read as undefined. reading the flag causes it to be cleared. (3) framing error (ferr): bit 2 of the sc0cr in uart mode, this flag indicates whether a frami ng error has occurred. a framing error is reported when a 0 is detected where a stop bit was expected . (the middle three of the 16 samples are used to determine the bit value.) reading the flag causes it to be cleared. during reception, only a single stop bit is detected regardless of the setting of the sblen bit in serial mode control register 2 (sc0mod2). operating mode error flag function oerr overrun error flag perr parity error flag uart ferr framing error flag oerr overrun error flag underrun error flag (wbuf = 1) perr fixed to 0 (wbuf = 0) i/o interface (sclk input) ferr fixed to 0 oerr undefined perr undefined i/o interface (sclk output) ferr fixed to 0 TMP1962C10BXBG 2006-02-21 tmp1962-296 14.2.12 bit transfer sequence the drchg bit in serial mode control register 2 (sc0mod2) determines whether the most significant bit (msb) or least significant bit (lsb) is transmitted first in i/o interface mode. the setting of the drchg bit cannot be modified while the sio is transferring data. 14.2.13 stop bit length bit 4 (sblen) in the sc0mod2 register determines the number of stop bits (1 or 2) used in uart mode. 14.2.14 status flag bit 8 (rbfll) in the sc0mod2 regi ster indicates whether receive bu ffer 2 is full (contains data) when double-buffering is enabled (sc0mod2.wbuf = 1). it is set to 1 once a received frame is transferred from receive buffer 1 to receive buffer 2. the rbfll bit is cleared to 0 when the cpu or dmac reads data from receive buffer 2. when wbuf = 0, the rbfll bit has no meaning; it should not be used as a status flag. bit 7 (tbemp) in the sc0m od2 register indicates whether transmit buffer 2 is empty when double-buffering is enabled (sc0mod2.wbuf = 1). it is set to 1 once a transmit frame is transferred from transmit buffer 2 to transmit buffer 1 (shift register ). the tbemp bit is cleared to 0 when the cpu or dmac stores data in transmit buffer 2. when wbuf = 0, the tbemp bit has no meaning; it should not be used as a status flag. 14.2.15 transmit/receive buffer configuration wbuf = 0 wbuf = 1 transmit single double uart receive double double transmit single double i/o interface (sclk input) receive double double transmit single double i/o interface (sclk output) receive single double TMP1962C10BXBG 2006-02-21 tmp1962-297 14.2.16 signal generation timing (1) uart mode receive operation mode 9 data bits 8 data bits with parity 8 data bits with no parity, 7 data bits with parity, 7 data bits with no parity interrupt middle of the first stop bit middle of the first stop bit middle of the first stop bit framing error middle of the stop bit middle of the stop bit middle of the stop bit parity error ? middle of the last bit (i.e., parity bit) middle of the last bit (i.e., parity bit) overrun error middle of the stop bit middl e of the stop bit middle of the stop bit transmit operation mode 9 data bits 8 data bits with parity 8 data bits with no parity, 7 data bits with parity, 7 data bits with no parity interrupt (wbuf = 0) immediately before the stop bit is shifted out immediately before the stop bit is shifted out immediately before the stop bit is shifted out interrupt (wbuf = 1) immediately after the frame is transferred to transmit buffer 1 (i.e., immediately before the stop bit is shifted out) immediately after the frame is transferred to transmit buffer 1 (i.e., immediately before the stop bit is shifted out) immediately after the frame is transferred to transmit buffer 1 (i.e., immediately before the stop bit is shifted out) (2) i/o interface mode receive operation sclk output mode immediately after the rising edge of the last sclk pulse interrupt (wbuf = 0) sclk input mode immediately after the rising or falling edge of the last sclk pulse, as programmed sclk output mode immediately after the rising edge of the last sclk pulse (i.e., immediately after the frame is transferred to receive buffer 2) or immediately after the frame is read from receive buffer 2 interrupt wbuf = 1) sclk input mode immediately after rising or falling edge of the last sclk pulse, as programmed (i.e., immediately af ter the frame is transferred to receive buffer 2) overrun error sclk input mode immediately after the rising or falling edge of the last sclk pulse, as programmed transmit operation sclk output mode immediately after the rising edge of the last sclk pulse interrupt (wbuf = 0) sclk input mode immediately after the rising or falling edge of the last sclk pulse, as programmed sclk output mode immediately after the rising edge of the last sclk pulse or immediately after the frame is transferred to transmit buffer 1 interrupt (wbuf = 1) sclk input mode immediately after rising or falling edge of the last sclk pulse, as programmed or immediately after the frame is transferred to transmit buffer 1 underrun error sclk input mode immediately after the rising or falling edge of the next sclk pulse, as programmed note 1: do not modify any control register during transmit or receive operations. note 2: do not disable receive operations by clearing the sc0mod0.rxe bit while any data is being received. TMP1962C10BXBG 2006-02-21 tmp1962-298 14.3 register description (channel 0) 7 6 5 4 3 2 1 0 bit symbol tb8 ctse rxe wu sm1 sm0 sc1 sc0 read/write r/w reset value 0 0 0 0 0 0 0 0 function bit 8 of a transmitted character 0: disables cts operation 1: enables cts operation receive control 0: disables receiver 1: enables receiver wake-up function 0: disabled 1: enabled serial transfer mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: ta6trg (timer) 01: baud rate generator 10: internal fsys/2 clock 11: external clock (sclk0 input) figure 14.6 serial mode control register 0 (sc0mod0, for sio0) 7 6 5 4 3 2 1 0 bit symbol i2s0 fdpx0 sioen read/write r/w r/w r/w reset value 0 0 0 function idle 0: off 1: on syn- chronous 0: half- duplex 1: full- duplex sio operation 0: disable 1: enable sioen: enables or disables the supply of clock pulses to the sio module , except for registers. figure 14.7 serial mode control register 1 (sc0mod1, for sio0) sc0mod0 (0xffff_f261) wake-up function 9-bit uart mode other modes 0 interrupt on every received frame 1 interrupt only when rb8 = 1 don?t care 0 disable (accepts data streams at all times) 1 enable handshake ( cts ) control note: in i/o interface mode, the serial control register (sc0cr) is used to select the clock source. sc0mod1 (0xffff_f266) note: first, ensure rxe is cleared to 0. then, configure the mode registers (sc0mod0, sc0mod1 and sc0mod2). finally, set rxe to 1. note: when configuring the sc0mod1 register, first set bit 5 (sioen) to 1 before programming other bits (i2so and fdpx0). TMP1962C10BXBG 2006-02-21 tmp1962-299 7 6 5 4 3 2 1 0 bit symbol tbemp rbfll txrun sblen drchg wbuf swrst1 swrst0 read/write r/w w w reset value 1 0 0 0 0 0 0 0 function transmit buffer empty flag 0: full 1: empty receive buffer empty flag 0: empty 1: full trans- mission-in-p rogress flag 0: stopped 1: n progress number of stop bits 0: 1 1: 2 bit sequence 0: lsb first 1: msb first double- buffering 0: disable 1: enable software reset a write of 10 followed by a write of 01 swrst[1:0]: a write of 10 followed by a write of 01 to this field resets the module, thus initializing the rxe bit in the sc0mod0, the tbemp, rbfll and txrun bits in the sc0mod2, the oerr, perr and ferr bits in the sc0cr, and the internal circuits. wbuf: enables or disables double-buffering for transmit (sclk output or input) or receive (sclk output) operation in i/o interface mode or transmit operation in uart mode. for any other operation, double-buffering is always enabled. drchg: specifies the bit tran sfer sequence in i/o interface mode. in uart mode, the lsb is always transferred first. txrun: a status flag indicating whether transmit shift operation is in progress. when this bit is set to 1, transmit operation is in progress. when this bit is cleared to 0, transmit operation is completed (if tbemp = 1) or the transmit buffer contains a next frame and is ready for transmission (if tbemp = 0). rbfll: a flag indicating whether receive buffer 2 is full. the rbfll bit is set to 1 once a received frame is transferred from receive buff er 1 to receive buffer 2. it is cleared when the cpu or dmac reads the frame. if double-buffering is disabled, the rbfll bit has no meaning. tbemp: a flag indicating whether transmit buffer 2 is empty. the tbemp bit is set to 1 once a frame is transferred from transmit buffer 2 to transmit buffer 1. it is cleared when the cpu or dmac writes a next frame to transmit buffer 2. if double-buffering is disabled, the tbemp bit has no meaning. sblen: specifies the number of transmit stop b its in uart mode. for receive operation, a single stop bit is used regardless of the setting of this bit. figure 14.8 serial mode control register 2 (sc0mod2, for sio0) sc0mod2 (0xffff_f265) note: if the module needs to be reset while it is transmi tting data, two consecutive so ftware reset sequences (i.e., 10, 01, 10, 01) must be programmed. TMP1962C10BXBG 2006-02-21 tmp1962-300 7 6 5 4 3 2 1 0 bit symbol rb8 even pe oerr perr ferr sclks ioc read/write r r/w r (cleared when read) r/w reset value 0 0 0 0 0 0 0 1: error has occurred. function bit 8 of a received character parity type 0: odd 1: even parity 0: disabled 1: enabled overrun parity/ underrun framing 0: sclk0 1: sclk0 0: baud rate generator 1: sclk0 input figure 14.9 serial control register (sc0cr, for sio0) sc0cr (0xffff_f262) input clock in i/o interface mode framing error flag parity error/underrun error flag overrun error flag 0 data is transmitted/received on the sclk0 rising edge. 1 data is transmitted/received on the sclk0 falling edge. active edge for the sclk0 input parity type 0 baud rate generator 1 sclk0 input 0 odd parity 1 even parity these bits are cleared to 0 when read. note 1: the sclks bit must be set to 0 for the sclk0 output. note 2: all error flags are cleared to 0 when read. TMP1962C10BXBG 2006-02-21 tmp1962-301 7 6 5 4 3 2 1 0 bit symbol ? br0adde br0ck1 br0ck0 br0s3 br0s2 br0s1 br0s0 read/write r/w reset value 0 0 0 0 0 0 0 0 function must be written as 0. n + (16 - k)/16 function 0: disable 1: enable 00: t0 01: t2 10: t8 11: t32 clock divisor value n clock source for baud rate generator 00 internal clock t0 01 internal clock t2 10 internal clock t8 11 internal clock t32 7 6 5 4 3 2 1 0 bit symbol br0k3 br0k2 br0k1 br0k0 read/write r/w reset value 0 0 0 0 function value of k in n + (16 - k)/16 clock divisor value for baud rate generator br0cr TMP1962C10BXBG 2006-02-21 tmp1962-302 7 6 5 4 3 2 1 0 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 (for transmit) sc0buf (0xffff_f263) 7 6 5 4 3 2 1 0 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (for receive) figure 14.11 serial transmit/receive buffer register (sc0buf, for sio0) TMP1962C10BXBG 2006-02-21 tmp1962-303 14.4 operating modes 14.4.1 mode 0 (i/o interface mode) mode 0 utilizes a synchronization clock (sclk), which can be configured for either output mode in which the sclk clock is driven out from the tmp1962 or input mode in which the sclk clock is supplied externally. (1) transmit operations sclk output mode when transmit double-buffering is disabled (s c0mod2.wbuf = 0) in sclk output mode, each time the cpu writes a frame to the transmit buffer, the eight bits of the frame is shifted out on the txd0 pin, and the synchronization clock is driven out from the sclk0 pin. when all the bits have been shifted out, the transmit-done interrupt (inttx0) is generated. when transmit double-buffering is enabled (s c0mod2.wbuf = 1), a frame is transferred from transmit buffer 2 to transmit buffer 1 (shift register) once the cpu writes the frame to transmit buffer 2 when the sio0 is not transmitting any data or once the last frame in transmit buffer 1 has been sent. at this time, the transmit buffer em pty flag (sc0mod2.tbemp) is set to 1 and the inttx0 is generated. if there is no data to be transferred from transmit buffer 2 to transmit buffer 1, however, sclk0 output is stopped without generating the inttx0 interrupt. transmit data write timing sclk0 output bit 0 bit 6 bit 7 bit 1 txd0 intt x 0 interrupt bit 0 tbrun when wbuf = 0 (double-buffering disabled) transmit data write timing sclk0 output bit 0 bit 6 bit 7 bit 1 txd0 inttx0 interrupt bit 0 tbrun tbemp when wbuf = 1 (double-buffering enabled) and transmit buffer 2 contains data TMP1962C10BXBG 2006-02-21 tmp1962-304 transmit data write timing sclk0 output bit 0 bit 6 bit 7 bit 1 txd0 intt x 0 interrupt tbrun tbemp when wbuf = 1 (double-buffering enabled) but transmit buffer 2 does not contain data figure 14.12 transmit operation in i/o interface mode (sclk0 output mode) sclk input mode when transmit double-buffering is disabled (sc0 mod2.wbuf = 0) in sclk input mode, the cpu must write a frame to the transmit buffer before th e sclk0 input is activated . the eight bits of a frame in the transmit buffer are shifted out on the txd0 pin, synchronous to the programmed edge of the sclk0 input. when all the bits have been sh ifted out, the transmit-done interrupt (inttx0) is generated. the cpu must load the next frame into the transmit buffer by point a (shown in the figure below). when transmit double-buffering is enabled (s c0mod2.wbuf = 1), a frame is transferred from transmit buffer 2 to transmit buffer 1 (shift register) once the cpu writes the frame to transmit buffer 2 before the sclk0 input is activated or once the last frame in transmit buffer 1 has been sent. at this time, the transmit buffer empty fl ag (sc0mod2.tbemp) is set to 1 and the inttx0 interrupt is generated. if the sclk0 input is activated before a frame is written to transmit buffer 2, however, the sio0 assumes an underrun error and sends eight bits of dummy data (ffh) although the internal bit counter starts counting. sclk0 input (sclks = 0: rising edge) sclk0 input (sclks = 1: falling edge) bit 0 bit 1 t xd0 intt x 0 interrupt bit 5 bit 6 bit 7 t ransmit data w rite timing bit 0 bit 1 a when wbuf = 0 (double-buffering disabled) TMP1962C10BXBG 2006-02-21 tmp1962-305 sclk0 input (sclks = 0: rising edge) sclk0 input (sclks = 1: falling edge) bit 0 bit 1 t xd0 intt x 0 interrupt bit 5 bit 6 bit 7 t ransmit data w rite timing bit 0 bit 1 a t brun t bemp when wbuf = 1 (double-buffering enabled) and transmit buffer 2 contains data sclk0 input (sclks = 0: rising edge) sclk0 input (sclks = 1: falling edge) bit 0 bit 1 t xd0 intt x 0 interrupt bit 5 bit 6 bit 7 t ransmit data w rite timing 11 a t brun t bemp perr (indicating an underrun error) when wbuf = 1 (double-buffering enabled) but transmit buffer 2 does not contain data figure 14.13 transmit operation in i/o interface mode (sclk0 input mode) TMP1962C10BXBG 2006-02-21 tmp1962-306 (2) receive operations sclk output mode when receive double-buffering is disabled (s c0mod2.wbuf = 0) in sclk output mode, each time the cpu picks up the frame in receive buffer 1, the synchroni zation clock is driven out from the sclk0 pin to shift the next frame into receive buffer 1. when a whol e 8-bit frame has been loaded into receive buffer 1, the intrx0 interrupt is generated. the sclk output is initiated by setting the sc0mod 0.rxe bit to 1. when receive double-buffering is enabled (sc0mod2.wbuf = 1), the frame received first is transferred to receive buffer 2 and then a next frame is received into receive buffer 1. once a frame is transferred from receive buffer 1 to receive buffer 2, the receive buffer full fl ag (sc0mod2.rbfll) is set to 1 and the intrx0 interrupt is generated. after a frame has been transferred to receive buffer 2, the cpu or dmac shou ld read it before all eight bits of a next frame are received. otherwise, the intrx0 interrupt is not generated and sclk0 output is stopped. in that state, when the cpu or dmac reads the frame from receive buffer 2, the next frame is transferred from receive buffer 1 to receive buffer 2, generating the intrx0 interrupt to restart receive operation. receive data read timing sclk0 output bit 0 bit 6 bit 7 bit 1 rxd0 intrx0 interrupt bit 0 when wbuf = 0 (double-buffering disabled) receive data read timing sclk0 output bit 0 bit 6 bit 7 bit 1 rxd0 intrx0 interrupt bit 0 bit7 rbfull when wbuf = 1 (double-buffering enab led) and receive buffer 2 is read receive data read timing sclk0 output bit 0 bit 6 bit 7 bit 1 rxd0 intrx0 interrupt bit7 rbfull when wbuf = 1 (double-buffering enable d) but receive buffer 2 is not read figure 14.14 receive operation in i/o interface mode (sclk0 output mode) TMP1962C10BXBG 2006-02-21 tmp1962-307 sclk input mode in sclk input mode, receive double-buffering is al ways enabled. a received frame is transferred to receive buffer 2 so that a next frame can be received continuously in to receive buffer 1. the intrx0 interrupt is generated every time a frame is transferred from receive buffer 1 to receive buffer 2. sclk0 input (sclks = 0: rising edge) sclk0 input (sclks = 1: falling edge) bit 0 bit 1 rxd0 intrx0 interrupt bit 5 bit 6 bit 7 receive data read timing bit 0 rbfull when receive buffer 2 is read sclk0 input (sclks = 0: rising edge) sclk0 input (sclks = 1: falling edge) bit 0 bit 1 rxd0 intrx0 interrupt bit 5 bit 6 bit 7 receive data read timing bit 0 rbfull oerr when receive buffer 2 is not read figure 14.15 receive operation in i/o interface mode (sclk0 input mode) note: regardless of whether sclk0 is in input mode or ou tput mode, the receiver must be enabled by setting the sc0mod0.rxe bit to 1 in order to perform receive operations. TMP1962C10BXBG 2006-02-21 tmp1962-308 (3) full-duplex transmit/receive operations setting bit 6 (fdpx0) in serial control register 1 (sc0mod1) to 1 enables full-duplex communication. sclk output mode when transmit/receive double-buffering is disabl ed (sc0mod2.wbuf = 0) in sclk output mode, each time the cpu writes a frame to the transmit buffer, the synchroni zation clock is driven out from the sclk0 pin to shift an 8-bit frame into receive buffer 1, generating the intrx0 interrupt. at the same time, the frame written to the transmit buffer is shifted out on the txd0 pin. when all the bits have been shifted out, the transmit-done interrupt (inttx0) is generated and sclk0 output is stopped. when the cpu subsequently picks up the frame in the receive buffer and writes a next frame to the transmit buffer, next transmit/receive operation starts, regardless of whether the cpu first reads the receive buffer or it first writes data to the transmit buffer. when transmit/receive double-buffering is en abled (sc0mod2.wbuf = 1), each time the cpu writes a frame to transmit buffer 2, the synchroni zation clock is driven out from the sclk0 pin to shift an 8-bit frame into receive bu ffer 1; it is then transferred to receive buffer 2, generating the intrx0 interrupt. at the same time, the frame stored in transmit buffer 1 is shifted out on the txd0 pin. when all the bits have been shifte d out, the transmit-done interrupt (inttx0) is generated and the next frame is transferred from transmit buffer 2 to transmit buffer 1. during the above sequence, sclk0 output is stopped if transmit buffer 2 does not contain data (sc0mod2.tbemp = 1) or if receive buffer 2 still contains data (sc0mod2.rbfll = 1). when the cpu subsequently picks up the frame in recei ve buffer 2 and writes a next frame to transmit buffer 2, sclk0 output is restarted so that next transmit/receive operation starts. TMP1962C10BXBG 2006-02-21 tmp1962-309 receive data read timing sclk0 output bit 0 bit 6 bit 7 bit 1 txd0 inttx0 interrupt bit 0 transmit data w rite timing intrx0 interrupt bit 5 bit 1 bit 0 bit 6 bit 7 bit 1 rxd0 bit 0 bit 5 bit 1 when wbuf = 0 (double-buffering disabled) receive data read timing sclk0 output bit 0 bit 6 bit 7 bit 1 txd0 inttx0 interrupt bit 0 transmit data w rite timing intrx0 interrupt bit 5 bit 1 bit 0 bit 6 bit 7 bit 1 rxd0 bit 0 bit 5 bit 1 when wbuf = 1 (double-buffering enabled) and no error occurs receive data read timing sclk0 output bit 0 bit 6 bit 7 bit 1 txd0 inttx0 interrupt transmit data w rite timing intrx0 interrupt bit 5 bit 0 bit 6 bit 7 bit 1 rxd0 bit 5 when wbuf = 1 (double-buffering enabled) and an error occurs figure 14.16 full-duplex transmit/receive operation in i/o interface mode (sclk0 output mode) TMP1962C10BXBG 2006-02-21 tmp1962-310 sclk input mode when transmit double-buffering is disabled (sc0mod2.wbuf = 0) in sclk input mode (receive double-buffering is always enabled in this mode), the cpu must write a frame to the transmit buffer before the sclk0 input is activated. the eight bits of a frame in the transmit buffer are shifted out on the txd0 pin, and the eight bits of a received fram e are shifted into receive buffer 1, synchronous to the programmed edge of the sclk0 input. wh en all the bits have been shifted out, the transmit-done interrupt (inttx0) is generated. when all the bits have been received, the frame is transferred from receive buffer 1 to receive buffer 2, generati ng the intrx0 interrupt. the cpu must load the next frame into the transmit buffer by point a (shown in the figure below). the cpu must also pick up the frame in receive buff er 2 before a next frame has been received. when transmit/receive double-buffering is enabled (sc0mod2.wbuf = 1), a frame is transferred from transmit buffer 2 to transmit buffer 1 once the last frame in transmit buffer 1 has been sent. at this time, the inttx0 interrupt is generated. when the 8-bit frame, received in parallel with transmission, has been shifted into receive buffer 1, it is transferre d to receive buffer 2, generating the intrx0 interrupt. when the slck0 is subsequently activated, the frame stored in transmit buffer 1 is shifted out while a next frame is receive d into receive buffer 1. if the cpu does not read the frame from receive buffer 2 before the last bit of a next frame is received, an overrun error occurs. if the cpu does not write a frame to transmit buffer 2 before the sclk0 input is subsequently activated, an underrun error occurs. TMP1962C10BXBG 2006-02-21 tmp1962-311 receive data read timing sclk0 output bit 0 bit 6 bit 7 bit 1 txd0 inttx0 interrupt bit 0 transmit data w rite timing intrx0 interrupt bit 5 bit 1 bit 0 bit 6 bit 7 bit 1 rxd0 bit 0 bit 5 bit 1 when wbuf = 0 (double-buffering disabled) receive data read timing sclk0 output bit 0 bit 6 bit 7 bit 1 txd0 inttx0 interrupt bit 0 transmit data w rite timing intrx0 interrupt bit 5 bit 1 bit 0 bit 6 bit 7 bit 1 rxd0 bit 0 bit 5 bit 1 when wbuf = 1 (double-buffering enabled) and no error occurs receive data read timing sclk0 output bit 0 bit 6 bit 7 bit 1 txd0 inttx0 interrupt bit 0 transmit data w rite timing intrx0 interrupt bit 5 bit 1 bit 0 bit 6 bit 7 bit 1 rxd0 bit 0 bit 5 bit 1 perr (underrun error) when wbuf = 1 (double-buffering enabled) and an error occurs figure 14.17 full-duplex transmit/receive operat ion in i/o interface mode (sclk0 input mode) TMP1962C10BXBG 2006-02-21 tmp1962-312 14.4.2 mode 1 (7-bit uart mode) setting the sm[1:0] field in the sc0mod0 to 01 puts the sio0 in 7-bit uart mode. in this mode of operation, the parity bit can be added to the transmitte d frame, and the receiver can perform a parity check on incoming data. parity can be enabled and disabled through the programming of the pe bit in the sc0cr. when pe = 1, the scr0 cr.even bit selects even or od d parity. the sblen bit in the sc0mod2 specifies the number of stop bits. example: transmitting 7-bit uart frames with an even-parity bit goes out first (transfer rate = 2400 bps @fc = 24.576 mhz) startbit 0123 5 46 even parity stop clocking conditions: system clock: high-speed (fc) high-speed clock gear: x1 (fc) prescaler clock: f periph /4 (f periph = f sys ) 7 6 5 4 3 2 1 0 pgcr ? ? ? ? ? ? 1 ? pgfc ? ? ? ? ? ? 1 ? configures the pg1 pin as txd0. sc0mod x 0 ? x 0 1 0 1 selects 7-bit uart mode. sc0cr x 1 1 x x x 0 0 selects even parity. br0cr 0 0 1 0 1 0 1 0 sets the transfer rate to 2400 bps. imc4lh ? ? 1 1 0 1 0 0 enables the inttx0 interrupt and sets its priority level to 4. sc0buf * * * * * * * * loads the transmit buffer with a frame. note: x = don't care, - = no change 14.4.3 mode 2 (8-bit uart mode) setting the sm[1:0] field in the sc0mod0 to 10 puts the sio0 in 8-bit uart mode. in this mode of operation, the parity bit can be added to the transmitte d frame, and the receiver can perform a parity check on incoming data. parity can be enabled and disabled through the programming of the pe bit in the sc0cr. when pe = 1, the scr0cr.even bit selects even or odd parity. example: transmitting 8-bit uart frames with an odd-parity bit goes out first (transfer rate = 9600 bps @fc = 24.576 mhz) startbit 0123 5 46 odd parity stop 7 clocking conditions: system clock: high-speed (fc) high-speed clock gear: x1 (fc) prescaler clock: f periph /4 (f periph = f sys ) TMP1962C10BXBG 2006-02-21 tmp1962-313 ? settings in the main routine 7 6 5 4 3 2 1 0 pgcr ? ? ? ? ? 0 ? ? pgfc ? ? ? ? ? 1 ? ? configures the pg2 pin as rxd0. sc0mod ? 0 0 x 1 0 0 1 selects 8-bit uart mode. sc0cr x 0 1 x x x 0 0 selects odd parity. br0cr 0 0 0 1 0 1 0 1 sets the transfer rate to 9600 bps. imc4ll ? ? 1 1 0 1 0 0 enables the intrx0 interrupt and sets its priority level to 4. sc0mod ? ? 1 x ? ? ? ? enables reception. ? example of interrupt routine processing intclr x x 0 1 0 0 0 0 clears the interrupt request. reg. sc0cr and 0x1c if reg. 0 then error checks for errors. reg. sc0buf reads received data. end of interrupt processing note: x = don't care, - = no change TMP1962C10BXBG 2006-02-21 tmp1962-314 14.4.4 mode 3 (9-bit uart mode) setting the sm[1:0] field in the sc0mod0 to 11 puts the sio0 in 9-bit uart mode. in this mode, a parity bit cannot be used; thus, parity should be disabled by clearing the sc0cr.pe bit to 0. for transmit operations, the most-significant bit (9th bit) is stored in bit 7 (tb8) in the sc0mod0. for receive operations, the most-significant bit is stored in bit 7 (rb8) in the sc0 cr. reads and writes of the transmit/receive frame must be done with the most -significant bit first, followed by the sc0buf. the sblen bit in the sc0mod2 specifi es the number of stop bits. wake-up feature in 9-bit uart mode, the receiver wake-up feature allows the slave station in a multidrop system to wake up whenever an address frame is receive d. setting the sc0mod0.wu bit enables the wake-up feature. when the sc0cr.rb8 bit has received an address/data flag bit set to 1, the receiver generates the intrx0 interrupt. figure 14.18 serial link using the wake-up function txd master slave 1 slave 2 slave 3 rxd txd rxd txd txd rxd rxd note: the slave controller's txd pin must be configured as an open-drain output by programming the ode register. TMP1962C10BXBG 2006-02-21 tmp1962-315 (1) put all the master and slave controllers in 9-bit uart mode. (2) enables the receiver in each slave controller by setting the sc0mod0.wu bit to 1. (3) the master controller transmits an 8-bit address frame (i.e, select code) that identifies a slave controller. the address character has the most-significant bit (bit 8) set to 1. slave controller select code start bit 0 1 2 3 5 46 s t o p 78 ?1? (4) each slave controller compares the received address to its station address and clears the wu bit if they match. (5) the master controller transmits a block of data to the selected slave controller (with sc0mod0.wu bit cleared). data frames have the most -significant bit (bit 8) cleared to 0. data ?0? start bit 0 1 2 3 5 46 s t o p 7bit 8 (6) slave controllers not addressed continue to monitor the data stream, but discard any frames with the most-significant bit (rb8) cleared, and thus do no t generate receive-done interrupts (intrx0). the addressed slave controller with its wu bit cleared can transmit data to the master controller to notify that it has successfully received the message. example: connecting a master station with tw o slave stations through a serial link using the f sys /2 clock as a serial clock txd master slave 1 slave 2 select code 00000001 rxd txd rxd txd rxd select code 00001010 protocol TMP1962C10BXBG 2006-02-21 tmp1962-316 ? master controller settings main routine pgcr ? ? ? ? ? 01 ? pgfc ? ? ? ? ? 11 ? configures the pg1 pin as tx d0 and the pg2 pin as rxd0. imc4ll ? ? 1 1 0 1 0 1 enables intrx0 and sets its interrupt level to 5. imc4lh ? ? 1 1 0 1 0 0 enables inttx0 and sets its interrupt level to 4. sc0mod0 1 0 1 0 1 1 1 0 selects 9-bit uart mode and selects f sys /2 as a serial clock. sc0buf 0 0 0 0 0 0 0 1 loads the select code for slave 1. interrupt routine (inttx0) intclr x x 0 1 0 0 0 1 clears the interrupt request. sc0mod0 0 ? ? ? ? ? ? ? clears the tb8 bit to 0. sc0buf * * * * * * * * loads the transmit data. end of interrupt processing ? slave controller settings main routine pdcr ? ? ? ? ? 01 ? pdfc ? ? ? ? ? 11 ? pgode ? ? ? ? ? ? 1 ? configures the pd0 pin as txd (open-drain output) and the pd1 pin as rxd. imc4ll ? ? 1 1 0 1 1 0 enables inttx0 and intrx0. imc4lh ? ? 1 10101 sc0mod0 0 0 1 1 1 1 1 0 selects 9-bit uart mode, selects f sys /2 as a serial clock and sets the wu bit to 1. interrupt routine (intrx0) intclr x x 0 1 0 0 0 0 clears the interrupt request. reg. sc0buf if reg. = select code then sc0mod0 ? ? ? 0 ? ? ? ? clears the wu bit to 0. TMP1962C10BXBG 2006-02-21 tmp1962-317 15. serial bus interface (sbi) the tmp1962 contains a serial bus interface (sbi) channel, which has the following two operating modes: ? i 2 c bus mode (with multi-master capability) ? clock-synchronous 8-bit sio mode in i 2 c bus mode, the sbi is connected to external devices via two pins, pf0 (sda) and pf1 (scl). in clock-synchronous 8-bit sio mode, the sbi is connected to external devices via three pins, pf2 (sck), pf2 (so) and pf1 (si). the following table shows the programming required to put the sbi in each operating mode. pfode TMP1962C10BXBG 2006-02-21 tmp1962-318 15.2 registers a listing of the registers used to control the sbi follows: ? serial bus interface control register 0 (sbicr0) ? serial bus interface control register 1 (sbicr1) ? serial bus interface control register 2 (sbicr2) ? serial bus interface data bu ffer register (sbidbr) ? i 2 c bus address register (i2car) ? serial bus interface status register (sbisr) ? serial bus interface baud rate register 0 (sbibr0) ? serial bus interface baud rate register 1 (sbibr1) the functions of these registers vary, depending on the mode in which the sbi is operating. for a detailed description of the registers, refer to section 15.4, "description of the registers used in i2c bus mode," and section 15.7, "description of the registers used in clock-synchronous 8-bit sio mode." 15.3 i 2 c bus mode data formats figure 15.2 shows the serial bus interface data formats used in i 2 c bus mode. figure 15.2 i 2 c-bus mode data formats note: s = start condition r/ w = direction bit ack = acknowledge bit p = stop condition r / w r / w s (a) addressing format (b) addressing format (with repeated start condition) (c) free data format (master-t ransmitter to slave-receiver) slave address data p s s sp p 8 bits 1 to 8 bits 1 once repeated 1 to 8 bits a c k slave address data data once once a c k a c k 8 bits 1 to 8 bits 8 bits 1 to 8 bits 11 1 1 1 1 8 bits 1 to 8 bits 1 to 8 bits data data data data a c k 1 1 1 slave address repeated once repeated repeated r / w a c k a c k a c k a c k a c k a c k TMP1962C10BXBG 2006-02-21 tmp1962-319 15.4 description of t he registers used in i 2 c bus mode this section provides a summary of the registers which control i 2 c bus operation and provide i 2 c bus status information for bus access/monitoring. serial bus interface control register 0 7 6 5 4 3 2 1 0 bit symbol sbien read/write r/w reset value 0 function sbi operation 0: disable 1: enable sbien: enables or disables the operation of the sbi. if the sbi is disabled, no clock pulses are supplied to the sbi registers other than the sbicr0, so that power consumption in the system can be reduced (only the sbicr0 can be read or written). to use the sbi, set the sbien bit to 1 before configuring other registers of the sbi. once the sbi operates, all settings in its registers are held if it is disabled. figure 15.3 i 2 c bus mode registers sbicr0 (0xffff_f254) note: bits 0 to 6 of the sbicr0 are read as 0. TMP1962C10BXBG 2006-02-21 tmp1962-320 serial bus interface control register 1 7 6 5 4 3 2 1 0 bit symbol bc2 bc1 bc0 ack sck2 sck1 sck0/ swrmon read/write w r/w w r/w reset value 0 0 0 0 0 0 1 function number of bits per transfer (note 1) ack clock pulse 0: no ack 1: ack internal scl output clock frequency (note 2) / software reset monitor on writes: sck[2:0] = internal scl output clock frequency 000 001 010 011 100 101 110 111 n=4 n=5 n=6 n=7 n=8 n=9 n=10 506 khz 281 khz 149 khz 77 khz 39 khz 20 khz 10 khz reserved system clock: fsys (= 40.5 mhz) clock gear : fc/1 frequency = [ hz ] on reads: swrmon = software reset monitor 0 software reset operation is in progress. 1 software reset operation is not in progress. number of bits per transfer ack = 0 ack = 1 TMP1962C10BXBG 2006-02-21 tmp1962-321 serial bus interface control register 2 7 6 5 4 3 2 1 0 bit symbol mst trx bb pin sbim1 sbim0 swrst1 swrst0 read/write w w (note 1) w (note 1) reset value 0 0 0 1 0 0 0 0 function master/ slave 0: slave 1: master transmit/ receive 0: receive 1: transmit start/ stop generation 0: stop condition 1: start condition ints interrupt clear 0: - 1: interrupt clear operating mode (note 2) 00: port mode 01: sio mode 10: i 2 c bus mode 11: reserved software reset a write of 10 followed by a write of 01 operating mode (note 2) 00 port mode (serial bus interface output disabled) 01 clock-synchronous 8-bit sio mode 10 i 2 c bus mode 11 reserved figure 15.5 i 2 c bus mode registers table 15.1 base clock resolutions @fsys = 40.5 mhz clock gear value gear[1:0] base clock resolution 00 (fc) fsys/2 2 (0.1 s) 01 (fc/2) fsys/2 3 (0.2 s) 10 (fc/4) fsys/2 4 (0.4 s) 11 (fc/8) fsys/2 5 (0.8 s) sbicr2 (0xffff_f250) note 1: reading this register causes it to function as a status register (sbisr). note 2: ensure that the bus is free before switching the op erating mode to port mode. ensure that the port is at logic high before switching from port mode to i 2 c bus or sio mode. TMP1962C10BXBG 2006-02-21 tmp1962-322 serial bus interface status register 7 6 5 4 3 2 1 0 bit symbol mst trx bb pin al aas ad0 lrb read/write r reset value 0 0 0 1 0 0 0 0 function master/ slave 0: slave 1: master transmit/ receive 0: receive 1: transmit i 2 c bus status 0: free 1: busy ints interrupt status 0: the interrupt is asserted. 1: the interrupt is not asserted arbitration lost 0: - 1: detected addressed as slave 0: - 1: detected general call 0: - 1: detected last received bit 0: 0 1: 1 last received bit 0 the last bit received was 0. 1 the last bit received was 1. addressed as slave 0 ? 1 the address on the bus matches the slave address or general-call address arbitration lost 0 ? 1 arbitration was lost to another master. figure 15.6 i 2 c bus mode registers sbisr (0xffff_f250) note: writing to this register causes it to function as a control register (sbicr2). TMP1962C10BXBG 2006-02-21 tmp1962-323 serial bus interface baud rate register 0 7 6 5 4 3 2 1 0 bit symbol i2sbi0 read/write r/w w reset value 0 0 function idle 0: off 1: on must be written as 0. sbi on/off in idle2 mode 0 off 1on serial bus interface baud rate register 1 7 6 5 4 3 2 1 0 bit symbol p4en read/write r/w reset value 0 function internal clock 0: off 1: on controls the internal baud rate generator 0 off 1on serial bus interface data buffer register 7 6 5 4 3 2 1 0 bit symbol db7 db6 db5 db4 db3 db2 db1 db0 read/write r (receive) / w (transmit) reset value undefined i 2 c bus address register 7 6 5 4 3 2 1 0 bit symbol sa6 sa5 sa4 sa3 sa2 sa1 sa0 als read/write w reset value 0 0 0 0 0 0 0 0 function when the sbi is addressed as a slave, this field specifies a 7-bit i 2 c-bus address to which the sbi responds. address recogniti on mode address recognition mode 0 recognizes the slave address. 1 does not recognize the slave address. figure 15.7 i 2 c bus mode registers sbibr0 (0xffff_f257) sbidbr (0xffff_f252) i2car (0xffff_f251) sbibr1 (0xffff_f256) note: in transmitter mode, data must be written to this register, with bit 7 being the most-significant bit (msb). TMP1962C10BXBG 2006-02-21 tmp1962-324 15.5 i 2 c bus mode configuration 15.5.1 acknowledgment mode setting the sbicr1.ack bit selects acknowledge mode. when operating as a master, the sbi generates a clock pulse for acknowledge automatically af ter each data. as a transmitter, the sbi releases the sda line during this acknowledge cycle so that the receiver of the data tran sfer can drive the sda line low to acknowledge receipt of the data. as a r eceiver, the sbi pulls the sda line low during the acknowledge cycle after each data has been received. clearing the sbicr1.ack bit selects non-acknowle dge mode. when operating as a master, the sbi does not generate acknowledge clock pulses. 15.5.2 number of bits per transfer the sbicr1.bc[2:0] field specifies the number of bits of the next data item to be transmitted or received. after a reset, this field is cleared to 000, causing a 7-bit slave address and the data direction (r/w) bit to be transferred in a p acket of eight bits. at other times, the sbicr1.bc[2:0] field keeps a previously programmed value. 15.5.3 serial clock (1) clock source the sbicr1.sck[2:0] field controls the maximum fre quency of the serial clock driven out on the scl pin in master mode, as illustrated below. figure 15.8 clock source t high t low 1/fscl t low = 2 n-1 /(fsys/4) t high = 2 n-1 /(fsys/4) + 4/(fsys/4) fscl = 1/(t low + t high ) sbi0cr1 TMP1962C10BXBG 2006-02-21 tmp1962-325 (2) clock synchronization clock synchronization is performed using the wired-and connection of all i 2 c-bus components to the bus. if two or more masters try to transfer messages on the i 2 c bus, the first to pull its clock line low wins the arbitration, overriding other masters producing a high on their clock lines. clock signals of two or more devices on the i 2 c-bus are synchronized to ensu re correct data transfers. figure 15.9 shows a depiction of the clock synchronization mechanism for the i 2 c bus with two masters. figure 15.9 clock synchronization example at point a, master a pulls its internal scl level low, bringing the scl bus line low. the high-to-low transition on the scl bus line causes master b to rese t its high-level counter and pull its internal scl level low. master a completes its low period at point b. howe ver, the low-to-high transition on its internal scl level does not change the state of the scl bus line if master b's internal scl level is still within its low period. therefore, master a enters a high wait state, where it does not st art counting off its high period. when master b has counted off its low period at point c, its internal scl level goes high, releasing the scl bus line (high). there will then be no difference between the internal scl levels and the state of the scl bus line, and both master a and master b start counting off their high periods. this way, a synchronized scl clock is generated with its high period determined by the master with the shortest clock high period and its low period determined by the one with the longest clock low period. 15.5.4 slave addressing and address recognition mode when the sbi is configured to oper ate as a slave, the sa[6:0] field in the i2car must be loaded with the 7-bit i 2 c-bus address to which the sbi is to respond. the als bit must be cleared for the sbi to recognize the incoming slave address. 15.5.5 configuring the sbi as a master or a slave setting the sbicr2.mst bit configures the sbi as a master, and clearing it configures the sbi as a slave. this bit is cleared by hardware when a stop condition has been detected and when arbitration for the i 2 c bus has been lost. internal scl level (master a) internal scl level (master b) scl bus line counter reset wait state start counting high period abc TMP1962C10BXBG 2006-02-21 tmp1962-326 15.5.6 configuring the sbi as a transmitter or a receiver the sbicr2.trx bit is set or cleared by hardware to configure the sbi as a transmitter or a receiver. as a slave, the sbi is put in either slave-receiver or slave-transmitter mode, depending on the value of the data direction (r/w) bit transmitted by the mast er. when the sbi is addre ssed as a slave, the trx bit reflects the value of the r/w bit. the trx bit is set or cleared on the following occasions: ? when transferring data using addressing format ? when the received slave address matches the value in the i2ccr ? when a general-call address is received; i.e., the eight bits following the start condition are all zeros. as a master, the sbi is put in either master-tra nsmitter or a master-receiver mode upon reception of an acknowledge from an addressed slave. the trx bit changes to the opposite value of the r/w bit sent by the sbi. if the sbi does not r eceive an acknowledge fro m a slave, the trx bit retains the previous value. the trx bit is cleared by hardware when a stop c ondition has been detected and when arbitration for the i 2 c bus has been lost. 15.5.7 generating start and stop conditions when the sbisr.bb bit is cleared, the bus is free. at this time, writing 1s to the mst, trx, bb and pin bits in the sbicr2 causes the sbi to generate a start condition on the bus and shift out 8-bit i 2 c-bus data. before generating a start condition, the ack bit must be set to 1. figure 15.10 generating a start condition and a slave address when the sbisr.bb bit is set, the bus is busy. wh en sbisr.bb = 1, writing 1s to the mst, trx and pin bits and a 0 to the bb bit causes the sbi to star t a sequence for generating a stop condition on the bus to abort the transfer. the mst, trx, bb and pi n bits should not be altered until a stop condition appears on the bus. figure 15.11 generating a stop condition the bb bit can be read to determine if the i 2 c bus is in use. the bb bit is set when a start condition is detected and cleared when a stop condition is detected. scl line start condition a6 slave address and direction bit a cknowledge signal 1 sda line 234567 8 9 a5 a4 a3 a2 a1 a0 r/w stop condition scl line sda line TMP1962C10BXBG 2006-02-21 tmp1962-327 15.5.8 asserting and deasserting interrupt requests when an sbi interrupt (ints) is generated, the pin b it in the sbicr2 is cleared to 0. while the pin bit is 0, the sbi pulls the scl line low. after transmission or receptio n of one data word on the i 2 c bus, the pin bit is automatically cleared. in transmitter mode, the pin bit is subsequently set to 1 each time the sbidbr is written. in receiver mode, the pin bit is set to 1 each time the sb idbr is read. it takes a period of t low for the scl line to be released after the pin bit is set. in address recognition mode (als = 0), the pin bit is cleared when the sbi is addressed as a slave and the received slave address matches the value in the i2 ccr or is all 0s (i.e., a general call). a write of 1 by software sets the pin bit, but a write of 0 has no effect on this bit. 15.5.9 sbi operating modes the sbim[1:0] field in the sbicr2 is used to select an operating mode of th e sbi. to configure the sbi for i 2 c bus mode, set the sbim[1:0] field to 10. a switch to port mode should only be attempted when the bus is free. 15.5.10 lost-arbitration detection monitor the i 2 c bus is a multi-master bus and has an arbitration procedure to ensure corr ect data transfers. a master may start a transfer only if the bus is free. a master that attempts to generate a start condition while the bus is busy loses bus arbitration, with no start condition occurring on the sda and scl lines. the i 2 c-bus arbitration takes place on the sda line. figure 15.12 shows the arbitration procedure for two ma sters. up until point a, the internal data levels of master a and master b are the same. at point a master b's internal data level makes a low-to-high transition while master a's internal data level remains at logic low. however, the sda bus line is held low because it is the wired-and of the two data outputs. when the scl bus clock goe s high at point b, the addressed slave device reads the data transmitted by master a (i.e., winning master). master b loses arbitration and switches off its data output stage, releas ing its sda line (high), so that it does not affect the data transfer initiated by the winning master. in cas e two competing masters have transmitted exactly the same first data word, the arbitration procedure continues with the second data word. figure 15.12 arbitration pr ocedure of two masters master b loses arbitration and connects a high output level to the bus. scl bus line internal sda level (master a ) internal sda level (master b) sda bus line ab TMP1962C10BXBG 2006-02-21 tmp1962-328 a master compares its internal data level to the actual level on the sda line at the rising edge of the scl clock. the master loses arbitration if there is a difference between these two values. the losing master sets the al bit in the sbisr to 1, which caus es the mst and trx bits in the same register to be cleared. that is, the losing master switches to slav e-receiver mode. the al bit is subsequently cleared when data is written to or read from the sbidbr and when the sbicr2 is programmed with new parameters. figure 15.13 master b loses arbitration (d7a = d7b, d6a = d6b) 15.5.11 slave address match monitor when acting as a slave-receiver, the als bit in th e i2ccr determines whether the sbi recognizes the incoming slave address or not. in address recognition m ode (i.e., als = 0), the aas bit in the sbisr is set when an incoming address over the i 2 c bus matches the value in the i2ccr or when the general-call address has been received. when als = 1, the aas bit is set when the fi rst data word has been received. the aas bit is cleared each time th e sbidbr is read or written. 15.5.12 general-call detection monitor when acting as a slave-receiver, the ad0 bit in the sbisr is set when a general-call address has been received. the general-call address is detected when the eight bits following a start condition are all zeros. the ad0 bit is cleared when a start or stop condition is detected on the bus. 15.5.13 last received bit monitor the lrb bit in the sbisr holds the value of the last bit received over the sda line at the rising edge of the scl clock. in acknowledge mode, reading this bit immediately after generation of the ints2 interrupt returns the value of the ack signal. TMP1962C10BXBG 2006-02-21 tmp1962-329 15.5.14 software reset the sbi provides a software reset, which permits recovery from system lockups caused by external noise. a software reset is performed by a write of 10 followed by a write of 01 to the swrst[1:0] field in the sbicr2. after a software reset, all control and stat us register bits are initialized to their reset values. upon resetting the sbi, the swrst[1:0] field is automatically cleared to 00. 15.5.15 serial bus interface data buffer register (sbidbr) the sbidbr is a data buffer interfacing to the i 2 c bus. all read and write operations to/from the i 2 c bus are done via this register. when the sbi is acting as a master, loading this regi ster with a slave address and a data direction bit causes a start condition to be generated. 15.5.16 i 2 c bus address register (i2car) when the sbi is configured as a sl ave, the sa[6:0] field in the i2car must be loaded with the 7-bit i 2 c-bus address to which the sbi is to respond. if the als bit in the i2car is cleared, the sbi recognizes a slave address transmitted by the master device, in terpreting incoming frame structures as per addressing format. if the als bit is set, the sbi does not recogni ze a slave address and interprets all frame structures as per free data format. 15.5.17 baud rate register (sbibr1) before the i 2 c bus can be used, the p4en bit in the sbibr1 must be set to enable the sbi internal baud rate generation logic. 15.5.18 idle setting register (sbibr0) the i2sbi bit in the sbibr0 determines whether the sbi is shut down or not when the tmp1962 is put in idle standby mode. this register must be programmed before executing an instruction for entering a standby mode.. note: a software reset causes the sbi operating mode to switch from i 2 c bus mode to clock-synchronous mode. TMP1962C10BXBG 2006-02-21 tmp1962-330 15.6 programming sequences in i 2 c bus mode 15.6.1 sbi initialization first, program the p4en bit in the sbibr1, and the ack and sck[2:0] bits in the sbicr1. set the sbibr1.p4en bit to 1 to enable the internal baud rate generation logic. write 0s to bits 7-5 and bit 3 in the sbicr1. next, program the i2car. the sa[6:0] field in the i2car define s the chip's slave address, and the als bit (bit 0) selects an address recognition mode. (the als bit must be cleared when using the addressing format.) next, program the sbicr2 to initially configure the sbi in slave-receiver mode; i.e., clear the mst, trx and bb bits to 0, set the pin bit to 1 and set the sbim[1:0] field to 10. write 00 to the swrst[1:0] field. 7 6 5 4 3 2 1 0 sbibr1 1 0 0 0 0 0 0 0 enables internal baud rate generator. sbicr1 0 0 0 x 0 x x x disables generation of ack and selects scl clock frequency. i2car x x x x x x x x loads a slave address and selects address recognition mode. sbicr2 0 0 0 1 1 0 0 0 configures the sbi in slave-receiver mode. note: x = don't care 15.6.2 generating a start condition and a slave address (1) master mode in master mode, the following steps are required to generate a start condition and a slave address on the i 2 c-bus. first, ensure that the bus is free (i.e., sbicr2.bb = 0). next, set the ack bit in the sbicr1 to enable generation of acknowledge clock pulses. th en, load the sbidbr with a slave address and a data direction bit to be transmitted via the i 2 c bus. when bb = 0, writing 1s to the mst, trx, bb and pin bits in the sbicr2 causes a start condition to be generated on the bus. following a start condition, the sbi generates scl clock pulses nine times: the sbi shifts out the contents of the sbidbr with the first eight scl clocks, and releases the sda line during the last (i.e., ninth) scl clock to receive an acknowledgement signal from the addressed slave. the ints interrupt request is generated on the fa lling edge of the ninth scl clock pulse, and the pin bit in the sbicr2 is cleared to 0. in master mode, the sbi holds the scl line low while the pin bit is 0. upon interrupt, the trx bit either remains set or is cleared accordi ng to the value of the transmitted direction bit, provided an acknowledg ement signal has been returned from the slave. TMP1962C10BXBG 2006-02-21 tmp1962-331 settings in main routine 7 6 5 4 3 2 1 0 reg. sbisr reg. reg. e 0x20 if reg. 0x00 ensures that the bus is free. then sbicr1 x x x 1 0 x x x selects acknowledgement mode. sbidr1 x x x x x x x x loads the slave address and a data direction bit. sbicr2 1 1 1 1 1 0 0 0 generates a start condition. ints interrupt routine intclr 0x14 clears the interrupt request. interrupt processing end of interrupt (2) slave mode in slave mode, the following steps are requir ed to receive a start condition and a slave address via the i 2 c bus. upon detection of a start condition, the sbi clocks in a 7-bit slave address and a data direction bit transmitted by the master during the first eight scl clock pulses. if the received slave address matches its own address in the i2car or is equal to the general-call address (00h), the sbi pulls the sda line low during the last (i.e., ninth) scl clock for acknowledgement. the ints interrupt request is generated on the fa lling edge of the ninth scl clock pulse, and the pin bit in the sbicr2 is cleared to 0. in slave mode, the sbi holds the scl line low while the pin bit is 0. figure 15.14 generation of a start condition and a slave address note: the user can only use a dma transfer: ? when there is only one master and only one slave on the i 2 c bus; and ? continuous transmission or reception is possible. scl start condition a6 slave address + direction bit a cknowledgme nt from slave 1 sda 2 34567 8 9 a5 a4 a3 a2 a1 a0 wr/ TMP1962C10BXBG 2006-02-21 tmp1962-332 15.6.3 transferring a data word each time a data word has been transmitted or recei ved, the ints interrupt is generated. it is the responsibility of the ints interrupt service routine to test the mst bit in the sbicr2 to determine whether the sbi is in master or slave mode. (1) master mode (sbicr2.mst = 1) if the mst bit in the sbicr2 is set, then test the trx bit in the same register to determine whether the sbi is in master-transmitter or master-receiver mode. master-transmitter mode (sbicr2.trx = 1) test the lrb bit in the sbisr. if the lrb bit is se t, that means the slave-receiver requires no further data to be sent from the master-transmitter. th e master-transmitter must then generate a stop condition as described later to stop transmission. if the lrb bit is cleared, that mean s the slave-receiver requires further data. if the number of bits per transfer is 8, then write the transmit data into the sbidbr. when using other data length, program the bc[2:0] and ack bits in the sbicr1, and then write the transmit data into the sbidbr. when the sbidbr is loaded, the pin bit in the sbisr is set to 1, and the transmit data is shifted out from the sda0 pin, clocked by the scl clock. once th e transfer is complete, the ints interrupt is generated, the pin bit is cleared, and the scl line is pulled low. to transmit further data, test the lrb bit again and repeat the above procedure. ints interrupt if mst = 0 then go to slave-mode processing if trx = 0 then go to receiver-mode processing if lrb = 0 then go to processing for generating a stop condition sbicr1 x x x x 0 x x x sets number of bits to be transmitted and specify whether ack is required. sbidbr x x x x x x x x loads the transmit data. end of interrupt processing note: x = don't care figure 15.15 sbicr1.bc[2:0] = 000 and sbicr1.ack = 1 (master-transmitter mode) scl pin write to sbidbr d7 a cknowledgement signal from receiver 1 sda pin 2 345678 9 d6 d5 d4 d3 d2 d1 TMP1962C10BXBG 2006-02-21 tmp1962-333 master-receiver mode (sbicr2.trx = 0) if the number of bits per transfer is 8, read th e sbidbr. when using other data length, program the bc[2:0] and ack bits in the sbicr1, and then read the sbidbr. the first read of the sbidbr is a dummy read because data has not yet been receive d. a dummy read returns an undefined value. upon this read, the scl line is released, the pin bit in the sbisr is set, and the scl clock is driven out to receive a data word into the sbidbr. the master-transmitter generates an acknowledgement signal (i.e., a low level) on the sda line following the last received bit. once the transfer is complete, the ints interrupt is generated, the pin bit is cleared, and the scl line is pulled low. each subsequent read from the sbidbr is accompanied by an scl clock pulse for a data word and an acknowledgement signal. figure 15.16 sbicr1.bc[2:0] = 000 and sbi cr1.ack = 1 (master-receiver mode) to prepare to terminate the data transfer, the ma ster-receiver must clear the ack bit in the sbicr1 immediately before the read of the second to last data word. this causes an acknowledge clock pulse to be suppressed on the last data word. when the transfer is complete, the ints interrupt is generated. after interrupt processing, the ints interrupt handler must set the bc[2:0] field in the sbicr1 to 001 and read the sbidbr, so that a clock is generated on the scl line once. with the ack bit cleared, the master-receiver holds the sda line high , which signals the end of transfer to the slave-transmitter. then, the sbi generates the ints interrupt again, whereupon the ints interrupt service routine must generate a stop condition to stop communication via the i 2 c bus. figure 15.17 terminating data transmission in master-receiver mode scl d7 a cknowledgement signal to transmitter 1 sda 2 345678 9 d6 d5 d4 d3 d2 d1 TMP1962C10BXBG 2006-02-21 tmp1962-334 example: when receiving n data words ints interrupt (after data transmission) 7 6 5 4 3 2 1 0 sbicr1 x x x x 0 x x x sets the number of bits to be received and specifies whether ack is required. reg. sbi0cbr dummy read end of interrupt ints interrupt (first to (n-2)th data reception) 7 6 5 4 3 2 1 0 reg. sbidbr reads the first to (n-2)th data words. end of interrupt ints interrupt ((n-1)th data reception) 7 6 5 4 3 2 1 0 sbi0cr1 x x x 0 0 x x x disables generation of acknowledgement clock. reg. sbidbr reads the (n-1)th data word. end of interrupt ints interrupt (nth data reception) 7 6 5 4 3 2 1 0 sbi0cr1 0 0 1 0 0 x x x generates a clock once. reg. sbidbr reads the nth data word. end of interrupt ints interrupt (after completing data reception) processing for generating stop c ondition terminates data transmission. end of interrupt x = don't care TMP1962C10BXBG 2006-02-21 tmp1962-335 (2) slave mode (sbicr2.mst = 0) if the mst bit in the sbicr2 is cl eared, the sbi is in slave mode. in slave mode, the sbi generates the ints interrupt on four occasions: 1) when the sbi has r eceived any slave address; 2) when the sbi has received a general-call address; 3) when a da ta transfer has been completed in response to a received slave address that matches its own address in the i2car; a nd 4) when a data transfer has been completed in response to a general-call. also, if the sbi, as a master, loses arbitration for the i 2 c bus, it switches to slave mode. if arbitration is lost during a data transfer, scl continues to be generated until the data word is complete; then the ints interrupt is generated. when the ints interrupt occurs, the pin bit in the sbisr is cleared, and the scl line is pulled low. when the sbidbr is read or written or when the pin bit is set back to 1, the scl line is released after a period of t low . processing to be done in slave mode varies, depending on whether or not the sbi has switched over to slave mode as a result of lost arbitration. test the al, trx, aas and ad0 bits in the sbisr to determine the processing required, as summarized in table 15.2 example: when the received slave address matches the sbi's own address and the data direction bit is 1 ints interrupt if trx = 0 then go to other processing if al = 1 then go to other processing if aas = 0 then go to other processing sbicr1 x x x 1 0 x x x specifies the number of bits to be transmitted. sbidbr x x x x 0 x x x loads the transmit data. note: x = don't care TMP1962C10BXBG 2006-02-21 tmp1962-336 table 15.2 processing in slave mode TMP1962C10BXBG 2006-02-21 tmp1962-337 15.6.4 generating a stop condition when the sbisr.bb bit is set, setting the mst, trx and pin bits in the sbicr2 to 1 and clearing the bb bit in the same register causes the sbi to start a sequence for generating a stop condition on the i 2 c bus. do not alter the contents of these bits until the stop condition is present on the bus. if another device is holding down the scl bus line, the sbi waits until the scl line is released (high) again; when scl is high, the sbi drives the sda pin high to generate a stop condition. 7 6 5 4 3 2 1 0 sbicr2 1 1 0 1 1 0 0 0 generates a stop condition. figure 15.18 generating a stop condition scl pin sda pin TMP1962C10BXBG 2006-02-21 tmp1962-338 15.6.5 repeated start condition a data transfer is always terminated by a stop condition. however, if a master still wishes to communicate on the bus, it can generate a repeated start condition and address another slave or change the data direction without first generating a stop condition. the following describes the steps required to generate a repeated start condition. first, clear the mst, trx and bb bits in the sbicr2 and set the pin bit in the same register to release the bus. this causes the sda pin to be held high and the scl pin to be released. because no stop condition is generated on the bus, other devices think that the bus is busy. then, poll the sbisr.bb bit until it is cleared to ensure that the scl pin is releas ed. next, poll the lrb bit until it is set to ensure that no other device is pulling the scl bus line low. once the bus is determined to be free this way, use the steps described in section 15.6.2 to generate a start condition. to satisfy the minimum setup time of the start condition, at least 4.7-s wait period (in normal mode) must be created by softwa re after the bus becomes free. 7 6 5 4 3 2 1 0 sbicr2 0 0 0 1 1 0 0 0 releases the bus. if sbisr TMP1962C10BXBG 2006-02-21 tmp1962-339 15.7 description of registers used in clock-synchronous 8-bit sio mode this section provides a summary of the registers which control clock-synchronous 8-bit sio operation and provides its status information for monitoring. serial bus interface control register 0 7 6 5 4 3 2 1 0 bit symbol sbien read/write r/w reset value 0 function sbi operation 0: disable 1: enable sbien: enables or disables the operation of the sbi. if the sbi is disabled, no clock pulses are supplied to the sbi registers other than the sbicr0, so that power consumption in the system can be reduced (only the sbicr0 can be read or written). to use the sbi, set the sbien bit to 1 before configuring other registers of the sbi. once the sbi operates, all settings in its registers are held if it is disabled. serial bus interface control register 1 7 6 5 4 3 2 1 0 bit symbol sios sioinh siom1 siom0 sck2 sck1 sck0 read/write w w r/w reset value 0 0 0 0 0 0 1 function start transfer 0: stop 1: start abort transfer 0: continue 1: abort transfer mode 00: transmit mode 01: reserved 10: transmit/receive mode 11: receive mode serial clock frequency on writes: sck[2:0] = serial clock frequency 000 001 010 011 100 101 110 111 n = 3 n = 4 n = 5 n = 6 n = 7 n = 8 n = 9 ? 1.27 633 316 158 79 40 20 mhz khz khz khz khz khz khz system clock: fsys (= 40.5 mhz) clock gear: fc/1 frequency = [ hz ] serial bus interface data buffer register 7 6 5 4 3 2 1 0 bit symbol db7 db6 db5 db4 db3 db2 db1 db0 read/write r (receive) /w (transmit) reset value undefined figure 15.20 sio mode registers sbicr1 (0xffff_f253) fs y s/4 2 n sbicr0 (0xffff_f254) note: bits 0 to 6 of the sbicr0 are read as 0. external clock note: clear the sios bit and set the sioinh bit before programming the transfer mode and serial clock frequency bits. sbidbr (0xffff_f252) TMP1962C10BXBG 2006-02-21 tmp1962-340 serial bus interface control register 2 7 6 5 4 3 2 1 0 bit symbol sbim1 sbim0 read/write w reset value 0 0 function sbi operating mode 00: port mode 01: sio mode 10: i 2 c bus mode 11: reserved serial bus interface register 7 6 5 4 3 2 1 0 bit symbol siof sef read/write r reset value 0 0 function serial transfer status monitor 0: termi-nat ed 1: in progress shift operation status monitor 0: termi nated 1: in progress serial bus interface baud rate register 0 7 6 5 4 3 2 1 0 bit symbol i2sbi read/write r/w w reset value 0 function idle 0: off 1: on must be written as 0. serial bus interface baud rate register 1 7 6 5 4 3 2 1 0 bit symbol p4en read/write r/w reset value 0 function internal clock 0: off 1: on figure 15.21 sio mode registers sbicr2 (0xffff_f250) sbisr (0xffff_f250) sbibr0 (0xffff_f257) sbibr1 (0xffff_f256) TMP1962C10BXBG 2006-02-21 tmp1962-341 15.7.1 serial clock (1) clock source the clock source for sio mode can be selected from internal and external clocks through the programming of the sck[2:0] field in the sbicr1. internal clocks one of the seven internal clocks can be used as a se rial clock, which is driven onto the sck pin. at the beginning of a transfer, the sck clock will start out at logic high. if software is slow and the reading of the received data or the writing of the transmit data cannot keep up with the serial clock rate, the sbi automatically inserts a wait period, as shown below. during this period, the serial clock is temporarily stopped to suspend a shift operation. figure 15.22 automatic wait insertion external clock (sbicr1.sck[2:0] = 111) if the sck[2:0] field in the sbicr1 contains 111, the sbi uses an external clock supplied from the sck pin as a serial clock. for proper shift operations, the clock high width and the clock low width must satisfy the following relationship. figure 15.23 maximum external clock frequency sck output so output writes of the transmit data 3 1 7 2 8 1 2 6 7 8 1 2 3 c 0 a b c automatically inserted wait period a 0 a 1 a 2 a 5 a 6 a 7 b 0 b 5 b 6 b 7 c 1 c 2 b 1 b 4 t sckh t sckl , t sckh > 8/fsys sck pin t sck TMP1962C10BXBG 2006-02-21 tmp1962-342 (2) shift edge types in transmit mode, leading-edge shift is used. in receive mode, trailing-edge shift is used. leading-edge shift every bit of sio data is shifted by the leading edge of the serial clock (falling edge of sck). trailing-edge shift every bit of sio data is shifted by the trailing edge of the serial clock (rising edge of sck). figure 15.24 shift edge types bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 76543210 * 7654321 ** 765432 *** 76543 **** 7654 *****765 ******76 ******7 so pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 6543210 * 543210 ** 0 ******* 10****** 210***** 3210 **** 43210 *** ******** 76543210 sck pin shift register sck pin si pin shift register (a) leading-edge shift (b) trailing-edge shift * : don't care TMP1962C10BXBG 2006-02-21 tmp1962-343 15.7.2 transfer modes the sbi supports three sio transfer modes: r eceive mode, transmit mode and transmit/receive mode. the siom[1:0] field in the sbicr1 is used to select a transfer mode. (1) 8-bit transmit mode configure the sio interface in transmit mode and write the tr ansmit data into the sbidbr. then setting the sios bit in the sbicr1 initiates a transmission. the contents of the sbidbr are moved to an internal shift register and then shifte d out on the so pin, with the least-significant bit (lsb) first, synchronous to the serial clock. once th e transmit data is transferred to the shift register, the sbidbr becomes empty, and the buffer-empty interrupt (intsbi) is generated. in internal clock mode, the sio interface will be in wait state (sck will stop) until the ints interrupt service routine provides the next transmit data to the sbidbr. once the sbidbr is loaded, the sio interface will automatically get out of the wait state. in external clock mode, the ints interrupt service r outine must provide the next transmit data to the sbidbr before the previous transmit data has been shifted out. therefore, the data rate is a function of the maximum latency between when the ints interrupt is generated and when the sbidbr is loaded by the interrupt service routine. at the beginning of a transmission, the value of the last bit of the previously transmitted byte appears on the so pin between when the sbisr.siof bit is set and when sck subsequently goes low. transmission can be terminated by the ints interr upt service routine clearing the sios bit to 0 or setting the sioinh bit to 1. if the sios bit is clear ed, the remaining bits in the sbidbr continue to be shifted out before transmission ends. in this case, software can check the sbisr.siof bit to determine whether transmission has come to an end (0 = end-of-transmission). if the sioinh bit is set, the ongoing transmission is aborted immediatel y, and the siof bit is cleared at that point. in external clock mode, the sios bit must be cleared before the sio interface begins shifting out the next transmit data. otherwise, the sio will stop after sending out dummy data. 7 6 5 4 3 2 1 0 sbicr1 0 1 0 0 0 x x x selects transmit mode. sbidbr x x x x x x x x writes the transmit data. sbicr1 1 0 0 0 0 x x x starts transmission. ints interrupt sbidbr x x x x x x x x writes the next transmit data. TMP1962C10BXBG 2006-02-21 tmp1962-344 figure 15.25 transmit mode example: mip16 code to terminate transm ission by sios (external clock mode) addiu r3, r0, 0x04 stest1: lb r2, (sbisr) ; if sbisr TMP1962C10BXBG 2006-02-21 tmp1962-345 figure 15.26 retention time of the last transmitted bit (2) 8-bit receive mode configure the sio interface in receive mode. then setting the sios bit in the sbicr1 enables reception. the receive data is clocked into the in ternal shift register vi a the si pin, with the least-significant bit (lsb) first, synchronous to the se rial clock. once the shift register is fully loaded, the received byte is transferred to the sbidbr, and the buffer-full interrupt (ints0) is generated. the ints interrupt service rou tine must then pick up the r eceived data from the sbidbr. in internal clock mode, the sio interface will be in wait state (sck will stop) until the ints interrupt service routine reads the data from the sbidbr. in external clock mode, shift operations continue, synchronous to the external clock. in this mode, the maximum data rate is a function of the maximum latency between when the ints interrupt is generated and when the sbidbr is read by the interrupt service routine. reception can be terminated by the ints interrupt service routine clearing the sios bit to 0 or setting the sioinh bit to 1. if the sios bit is clear ed, reception continues until the shift register is fully loaded and transferred to the sbidbr. in this case, software can check the sbisr.siof bit to determine whether reception has come to an end (0 = end-of-reception). if the sioinh bit is set, the ongoing reception is aborted immediat ely, and the siof bit is cleared at that point. (the received data becomes invalid; there is no need to read it out.) 7 6 5 4 3 2 1 0 sbicr1 0 1 1 1 0 x x x selects receive mode. sbicr1 1 0 1 1 0 0 0 0 starts reception. ints interrupt reg. sbidbr reads the received data. bit 7 sck pin siof so pin bit 6 t sodh = min. 3.5/f sys /2 [s] note: the contents of the sbidbr are not preserved after changing the transfer mode. before changing the transfer mode, clear the sios bit to complete the ongoing reception and have the ints interrupt service routine pick up the last received data. TMP1962C10BXBG 2006-02-21 tmp1962-346 figure 15.27 receive mode (internal clock mode) (3) 8-bit transmit/receive mode configure the sio interface in transmit/receive m ode and write the transmit data into the sbidbr. then setting the sios bit in the sbicr1 initiates transmission and reception. the transmit data is shifted out through the so pin, with the least-signif icant bit (lsb) first, with the falling edge of the serial clock, while at the same time the receive data is shifted in through the si pin with the rising edge of the serial clock. once the shift register is fu lly loaded with ei ght bits of the received data, it is transferred to the sbidbr, and the ints interrupt is generated. the ints interrupt service routine must then pick up the received data from the sb idbr and writes the next transmit data into the sbidbr. because the sbidbr is shared between tr ansmit and receive operations, the received data must be read before the next transmit data is written. in internal clock mode, the sio interface will be in wait state (sck will stop) after a read of the received data until a write of the transmit data. in external clock mode, shift operations continue, synchronous to the external clock. therefore, software must read the received data and write the transmit data before the next shift operation begins. in this mode, the maximum data rate is a function of the maximum latency between when the ints interrupt is generated and when the interrupt service routine reads th e received data and writes the transmit data. at the beginning of a transmission, the value of the last bit of the previously transmitted byte appears on the so pin between when the sbisr.siof bit is set and when sck subsequently goes low. transmission/reception can be terminated by the ints interrupt serv ice routine clearing the sios bit to 0 or setting the sioinh bit to 1. if the sios bit is cleared, reception continues until the shift register is fully loaded and transferred to th e sbidbr. in this case, software can check the sbisr.siof bit to determine whether transmission/reception has come to an end (0 = end-of-reception/transmission). if the sioinh bit is set, the ongoing tran smission/reception is aborted immediately, and the siof bit is cleared at that point. sbidbr ints interrupt request TMP1962C10BXBG 2006-02-21 tmp1962-347 figure 15.28 receive/transmit mode (internal clock mode) figure 15.29 retention time of the tran smit data in receive/transmit mode 7 6 5 4 3 2 1 0 sbicr1 0 1 1 0 0 x x x selects receive/transmit mode. sbidbr x x x x x x x x writes the transmit data. sbicr1 1 0 1 0 0 x x x starts reception/transmission. ints interrupt reg. sbiodbr reads the received data. sbidbr x x x x x x x x writes the transmit data. sbidbr ints interrupt request TMP1962C10BXBG 2006-02-21 tmp1962-348 16. analog-to-digital converter (adc) the tmp1962 has a 24-channel, mu ltiplexed-input, 10-bit successive-a pproximation an alog-to-digital converter (adc). figure 16.1 shows a block diagram of the adc. the 24 analog input channels (an0-an23) can be used as general-purpose digital inputs if not needed as analog channels. a/d monitor function interrupt interrupt request (intad) an23 (p97) an15 (p87) an7 (p77) an0 (p70) comparator vrefh vrefl internal data bus multiplexer sample-and- hold admod1 scan repeat interrupt interval busy end + ? internal data bus internal data bus channel selection control circuit adtrg a/d conversion result registers adreg08l~7fl adreg08h~7fh d/a converter normal a/d converter control circuit admod0 admod3 a/d conversion result register com p are circuit compare register a/d monitor function control a/d start control admod4 ta0/ctrg ads adscn vref figure 16.1 adc block diagram note: please confirm the thing that the movement of the a/d converter has stopped when changing to idle and the stop mode. TMP1962C10BXBG 2006-02-21 tmp1962-349 16.1 register description the adc has five mode control registers (admod0,admmod3,admod4). figure 16.2 to figure 16.6 show the registers available in the adc. a/d mode control register 0 7 6 5 4 3 2 1 0 bit symbol eocfn adbfn it m1 itm0 repeat scan ads read/write r r/w reset value 0 0 0 0 0 0 0 function end-of-conv ersion flag 0: during conver-sion 1:comp-leted a/d conversion busy flag 0: idle 1: during conver-sion interrupt in fixed-chan nel continuous conversion mode interrupt in fixed-chan nel continuous conversion mode continuous conversion mode 0: single 1:conti-nuous channel scan mode 0:fixed-ch annel 1: channel scan a/d conversion start 0: don't care 1: start this bit is always read as 0. interrupt in fixed-channel continuous conversion mode fixed-channel conti nuous conversion mode scan = 0, repeat = 1 00 generates intad interrupt when a single conversion has been completed. 01 generates intad interrupt when a sequence of four conversions has been completed. 10 generates intad interrupt when a sequence of eight conversions has been completed. 11 setting prohibited figure 16.2 a/d conversion registers a dmod0 (0xffff_f31b) TMP1962C10BXBG 2006-02-21 tmp1962-350 a/d mode control register 1 7 6 5 4 3 2 1 0 bit symbol vrefon i2ad adscn adch4 adch3 adch2 adch1 adch0 read/write r/w reset value 0 0 0 0 0 0 0 0 function vref control 0: off 1: on idle 0: off 1: on channel scan mode 0: 4-channel 1: 8-channel analog input channel select analog input channel select TMP1962C10BXBG 2006-02-21 tmp1962-351 a/d mode control register 3 7 6 5 4 3 2 1 0 bit symbol adobic regs2 regs1 reg ( 0 adobsv read/write r/w r/w reset value 0 0 0 0 0 0 0 function must be written as 0. a/d monitor interrupt setting 0: less than compare register 1: greater than compare register must be written as 0. a/d conversion result register to be compared with compare register when a/d monitor function is enabled a/d monitor function 0: disable 1: enable TMP1962C10BXBG 2006-02-21 tmp1962-352 a/d conversion result low register 08 7 6 5 4 3 2 1 0 bit symbol adr01 adr00 ovr0 adr0rf read/write r r r reset value undefined 0 0 function lower 2 bits of an a/d conversion result overrun flag 0: no overrun 1: overrun conversion result store flag 1: stored a/d conversion result high register 08 7 6 5 4 3 2 1 0 bit symbol adr09 adr08 adr07 adr06 adr05 adr04 adr03 adr02 read/write r reset value undefined function upper 8 bits of an a/d conversion result a/d conversion result low register 19 7 6 5 4 3 2 1 0 bit symbol adr11 adr10 ovr1 adr1rf read/write r r r reset value ? 0 0 function lower 2 bits of an a/d conversion result overrun flag 0: no overrun 1: overrun conversion result store flag 1: stored a/d conversion result high register 19 7 6 5 4 3 2 1 0 bit symbol adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 read/write r reset value undefined function upper 8 bits of an a/d conversion result 9876543210 channel x conversion result bits 76543210 765 4 3 2 10 ? bits 5-2 are always read as 1. ? bit 0 (adrxrf), when set, indicates that the conv ersion result has been stored in the adregxh/l register pair. this bit is cleared when the adregxl is read. ? bit 1 (ovrx) indicates an overrun error. this bit is set if a next conversion result is written to the adregxh/l before both the adregxh and adregxl are read. reading the flag causes it to be cleared. figure 16.4 a/d conversion registers a dreg08l (0xffff_f303) a dreg08h (0xffff_f302) a dreg19h (0xffff_f300) a dreg19l (0xffff_f301) a dregxh adregxl TMP1962C10BXBG 2006-02-21 tmp1962-353 a/d conversion result low register 2a 7 6 5 4 3 2 1 0 bit symbol adr21 adr20 ovr2 adr2rf read/write r r r reset value undefined 0 0 function lower 2 bits of an a/d conversion result overrun flag 0: no overrun 1: overrun conversion result store flag 1: stored a/d conversion result high register 2a 7 6 5 4 3 2 1 0 bit symbol adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 read/write r reset value undefined function upper 8 bits of an a/d conversion result a/d conversion result low register 3b 7 6 5 4 3 2 1 0 bit symbol adr31 adr30 ovr3 adr3rf read/write r r r reset value undefined 0 0 function lower 2 bits of an a/d conversion result overrun flag 0: no overrun 1: overrun conversion result store flag 1: stored a/d conversion result high register 3b 7 6 5 4 3 2 1 0 bit symbol adr39 adr38 adr37 adr36 adr35 adr34 adr33 adr32 read/write r reset value undefined function upper 8 bits of an a/d conversion result 9876543210 channel x conversion result bits 76543210 765 4 3 2 10 ? bits 5-2 are always read as 1. ? bit 0 (adrxrf), when set, indicates that the conv ersion result has been stored in the adregxh/l register pair. this bit is cleared when the adregxl is read. ? bit 1 (ovrx) indicates an overrun error. this bit is set if a next conversion result is written to the adregxh/l before both the adregxh and adregxl are read. reading the flag causes it to be cleared. figure 16.5 a/d conversion registers a dreg2al (0xffff_f307) a dreg2ah (0xffff_f306) a dreg3bl (0xffff_f305) a dreg3bh (0xffff_f304) a dregxh adregxl TMP1962C10BXBG 2006-02-21 tmp1962-354 a/d conversion result low register 4c 7 6 5 4 3 2 1 0 bit symbol adr41 adr40 ovr4 adr4rf read/write r r r reset value undefined 0 0 function lower 2 bits of an a/d conversion result overrun flag 0: no overrun 1: overrun conversion result store flag 1: stored a/d conversion result high register 4c 7 6 5 4 3 2 1 0 bit symbol adr49 adr48 adr47 adr46 adr45 adr44 adr43 adr42 read/write r reset value undefined function upper 8 bits of an a/d conversion result a/d conversion result low register 5d 7 6 5 4 3 2 1 0 bit symbol adr51 adr50 ovr5 adr5rf read/write r r r reset value undefined 0 0 function lower 2 bits of an a/d conversion result overrun flag 0: no overrun 1: overrun conversion result store flag 1: stored a/d conversion result high register 5d 7 6 5 4 3 2 1 0 bit symbol adr59 adr58 adr57 adr56 adr55 adr54 adr53 adr52 read/write r reset value undefined function upper 8 bits of an a/d conversion result 9876543210 channel x conversion result bits 76543210 765 4 3 2 10 ? bits 5-2 are always read as 1. ? bit 0 (adrxrf), when set, indicates that the conv ersion result has been stored in the adregxh/l register pair. this bit is cleared when the adregxl is read. ? bit 1 (ovrx) indicates an overrun error. this bit is set if a next conversion result is written to the adregxh/l before both the adregxh and adregxl are read. reading the flag causes it to be cleared. a dreg4cl (0xffff_f30b) a dreg4ch (0xffff_f30a) a dreg5dl (0xffff_f309) a dreg5dh (0xffff_f308) a dregxh adregxl TMP1962C10BXBG 2006-02-21 tmp1962-355 a/d conversion result low register 6e 7 6 5 4 3 2 1 0 bit symbol adr61 adr60 ovr6 adr6rf read/write r r r reset value undefined 0 0 function lower 2 bits of an a/d conversion result overrun flag 0: no overrun 1: overrun conversion result store flag 1: stored a/d conversion result high register 6e 7 6 5 4 3 2 1 0 bit symbol adr69 adr68 adr67 adr66 adr65 adr64 adr63 adr62 read/write r reset value undefined function upper 8 bits of an a/d conversion result a/d conversion result low register 7f 7 6 5 4 3 2 1 0 bit symbol adr71 adr70 ovr7 adr7rf read/write r r r reset value undefined 0 0 function lower 2 bits of an a/d conversion result overrun flag 0: no overrun 1: overrun conversion result store flag 1: stored a/d conversion result high register 7f 7 6 5 4 3 2 1 0 bit symbol adr79 adr78 adr77 adr76 adr75 adr74 adr73 adr72 read/write r reset value undefined function upper 8 bits of an a/d conversion result 9876543210 channel x conversion result bits 76543210 765 4 3 2 10 ? bits 5-2 are always read as 1. ? bit 0 (adrxrf), when set, indicates that the conv ersion result has been stored in the adregxh/l register pair. this bit is cleared when the adregxl is read. ? bit 1 (ovrx) indicates an overrun error. this bit is set if a next conversion result is written to the adregxh/l before both the adregxh and adregxl are read. reading the flag causes it to be cleared. a dreg6el (0xffff_f30f) a dreg6eh (0xffff_f30e) a dreg7fl (0xffff_f30d) a dreg7fh (0xffff_f30c) a dregxh adregxl TMP1962C10BXBG 2006-02-21 tmp1962-356 a/d conversion result compare low register 7 6 5 4 3 2 1 0 bit symbol adr21 adr20 read/write r/w reset value 0 function lower 2 bits of a value to be compared with an a/d conversion result a/d conversion result compare high register 7 6 5 4 3 2 1 0 bit symbol adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 read/write r/w reset value 0 function upper 8 bits of a value to be compared with an a/d conversion result a dcomregl (0xffff_f317) a dcomregh (0xffff_f316) note: disable the a/d monitor function (set admod3.adobsv to 0) before attempting to set or modify the contents of these registers. TMP1962C10BXBG 2006-02-21 tmp1962-357 a/d conversion clock setting register 7 6 5 4 3 2 1 0 bit symbol adclk2 adclk1 adclk0 read/write r/w r/w r/w reset value 0 0 0 function a/d prescaler output 000: fc 1xx: fc/16 001: fc/2 010: fc/4 011: fc/8 figure 16.6 a/d conversion registers a dclk (0xffff_f31c) note 1: a/d conversion is performed at the clock frequency selected in the above register. to assure conversion accuracy, however, the conversion clock frequency must not exceed 20.25 mhz. fc = 40.5mhz TMP1962C10BXBG 2006-02-21 tmp1962-358 16.2 operation 16.2.1 analog reference voltages the vrefh and vrefl pins provide the referen ce voltages for the adc. clearing the vrefon bit in the admod1 turns off the switch between vrefh and vrefl. once the vref on bit is cleared, the internal reference voltage requires a recovery time of 3 s (t.b.d.) to stabilize after the vrefon bit is again set to 1. the ads bit in the admod0 must then be set to initiate an conversion. ? fixed-channel mode (admod0.scan = 0) when the scan bit in the admod0 is cleared, the adc runs conversions on a single input channel selected from an0-an23 via the adch[4:0] field in the admod1. ? channel scan mode (admod0.scan = 1) when the scan bit in the admod0 is set, the adc runs conversions on sequential channels in a specific group selected via th e adch[4:0] field in the admod1. after a reset, the admod0.scan bit defaults to 0, and the admod1.adch[3:0] field defaults to 0000. thus, the an0 pin is selected as the conversion channel. the an0-an23 pins can be used as general-purpose input ports if not used as analog input channels. 16.2.2 starting an a/d conversion the adc initiates conversion when the ads bit in the admod0 is set. the adhtg bits in the admod4 enable a hardware trigger source for conv ersion, respectively. when the adhs bit in the admod4 is cleared to 0, conversion is triggered by a falling edge applied to adtrg pin. when the adhs bit is set to 1, conversion is triggered by a ta0trg output from 8-bit timer 0. when conversion starts, the busy flag (admod0.adbf) is set. . TMP1962C10BXBG 2006-02-21 tmp1962-359 16.2.3 conversion modes and conversion-done interrupts the adc supports the following four conversion modes. for a normal a/d conversion, the repeat and scan bits in the admod0 select one of the four conversion modes. for a high-priority a/d conversion, the adc only supports fixed-channel single conversion mode, regardless of the settings of the repeat and scan bits. ? fixed-channel single conversion mode ? channel scan single conversion mode ? fixed-channel continuous conversion mode ? channel scan continuous conversion mode the repeat and scan bits in the admod0 sel ect the conversion mode. once a conversion is started, the adbfn bit in the admod0 is set to 1. the adc generates the intad interrupt and sets the eocf bit in the admod0 at the end of th e specified conversion pr ocess. if repeat = 0, the adbfn bit is cleared when the adc sets the eocf bit. if repeat = 1, the adc continues conversion without clearing adbfn. 1) fixed-channel single conversion mode this mode is selected by programming the repeat and scan bits in the admod0 to 00. in this mode, the adc performs a single conversion on a single selected channel. when a conversion is completed, the adc sets the admod0.eocf bit, clears the admod0.adbf bit and generates the intad interrupt. the eocf bit is cleared when it is read. 2) channel scan single conversion mode this mode is selected by programming the repeat and scan bits in the admod0 to 01. in this mode, the adc performs a single conversion on each of a selected group of channels. when a single conversion sequence is completed, the ad c sets the admod0.eocf bit, clears the admod0.adbf bit and generates the intad interrupt. the eocf bit is cleared when it is read. 3) fixed-channel continuous conversion mode this mode is selected by programming the repeat and scan bits in the admod0 to 10. in this mode, the adc repeatedly conver ts a single selected channel. when a conversion process is completed, the adc sets the admod.eocf bit. the admod0 .adbf bit remains set. the itm[1:0] bits in the admod0 control interrupt generation in this mode. the timing when the eocf bit is set also depends on the itm[1:0] bits . the eocf bit is cleared when it is read. if the itm[1:0] field is set to 00, the adc generate s an interrupt after each conversion. the results of conversion are always stored in the adreg08 register pair. the eocf bit is set when the adc stores the results in the adreg08. if the itm[1:0] field is set to 01, the adc generates an interrupt after every four conversions. the results of conversions are sequentially stored in the adreg08 to adreg3b register pairs, in that order. the eocf bit is set when the adc stores the results in the adreg3b. the next conversion results are again stored in the adreg08, and so on. the eocf bit is cleared when it is read. TMP1962C10BXBG 2006-02-21 tmp1962-360 if the itm[1:0] field is set to 10, the adc generates an interrupt after every eight conversions. the results of conversions are sequentially stored in the adreg08 to adreg7f register pairs, in that order. the eocf bit is set when the adc stores the results in the adreg7 f. the next conversion results are again stored in the adreg08, and so on. the eocf bit is cleared when it is read. 4) channel scan continuous conversion mode this mode is selected by programming the repeat and scan bits in the admod0 to 11. in this mode, the adc repeatedly converts the selected group of channels. when a single conversion sequence is completed, the adc sets the adm od0.eocf bit and generates the intad interrupt. the admod0.adbf bit remains set. the eo cf bit is cleared when it is read. in continuous conversion modes (3) and 4)), clearing the admod0.repeat bit stops the conversion sequence after the ongoing conversion process is completed. the admod0.adbf bit is cleared. before putting the tmp1962 in any standby mode (idle or stop), check the adc is being disabled (or disable the adc). TMP1962C10BXBG 2006-02-21 tmp1962-361 interrupt request generation and flag setting in each a/d conversion mode admod0 mode interrupt request generation eocf set timing (note) adbf (upon generation of interrupt) itm1:0 repeat scan fixed-channel single conversion mode after a conversion after a conversion 0 0 0 after every conversion after every conversion 1 00 after every four conversions after every four conversions 1 01 fixed-channel continuous conversion mode after every eight conversions after every eight conversions 1 10 1 0 channel scan single conversion mode after a scan conversion sequence after a scan conversion sequence 0 0 1 channel scan continuous conversion mode after each scan conversion sequence after each scan conversion sequence 1 1 1 16.2.4 high-priority conversion mode the adc can perform a high-priority a/d conversion while it is performing a normal a/d conversion sequence. a high-priority a/d conversion can be in itiated by setting the hpadce bit in the admod2 to 1. it is also triggered by a hardware resource if so enabled using the hadhtg and hadhs bits in the admod4. if a high-priority conversion is triggered during a normal conversion, the adc stores the results of conversion for the current channel and then begins a single high-priority conversion for the channel specified with the hpadch[4:0] bits in the admod2. upon the completion of the high-priority conversion, the adc stores the results of the conversion in the adregsp, generates the end-of-high-priority-conversion interrupt, and then resumes the suspended normal conversion with the next channel. while a high-priority conversion is being performed, a trigger for another high-priority conversion is ignored. for example, suppose the adc is performing conversions for an0-an8 in channel scan continuous conversion mode. if the hpadce bit is set to 1 while the adc is converting data for an3, it completes conversion for an3 and then conver ts data for the channel specified with hpadch[4:0]. after storing the results of conversion in the adregsp, the adc resumes the suspended normal conversion sequence, beginning with conversion for an4. 16.2.5 a/d monitor function when the adobsv bit in the admod3 is set to 1, the a/d monitor function is enabled. this function generates an interrupt if the value stored in the speci fied a/d conversion result register pair (specified with the regs[3:0] bits in the admod3) is greater or less (depending on admod3.adobic) than the contents of the compare register pair. the adc perfor ms this comparison each time it stores results to the specified register pair. the conversion result register pair used for the a/d monitor function is usually not read in the program, so that its overrun flag (ovrn) and conversion result storage flag (adrnrf) are always set. when using the a/d monitor function, therefore, do not use flags for the register pair assigned for comparison. note: eocf is cleared when it is read. TMP1962C10BXBG 2006-02-21 tmp1962-362 16.2.6 conversion time the a/d conversion clock can be se lected from a/d prescaler output t0/2, t0/4, t0/8, t0/16 and t0/32 through the programming of the adclk[2:0] field in the adclk register. to assure conversion accuracy, the conversion clock frequency must not excee d 20.25 mhz, i.e., conversion time must be no shorter than 7.95 s. 16.2.7 storing and reading the a/d conversion result conversion results are loaded into conversion result high/low register pairs (adreg08h/l to adreg7fh/l). in fixed-channel continuous conversion mode, conversion data goes into the adreg08h/l to adreg7fh/l sequentially. if the itm[1:0] field is set to 00, so that the adc generates an interrupt after each conversion, conversion data is stored in the adreg08h/l only. if the itm[1:0] field is set to 01, so that the adc generates an interrupt after every fo ur conversions, conversion data goes into the adreg08h/l to adreg3bh/l sequentially. table 16.1 shows the relationships between the analog input channels and the a/d conversion result registers. table 16.1 relationships between analog input channels and a/d conversion result registers a/d conversion result registers analog input channel (port a) modes other than fixed-channel continuous conversion mode fixed-channel continuous conversion mode (for each sequence of eight conversions) an0 adreg08h/l an1 adreg19h/l an2 adreg2ah/l an3 adreg3bh/l an4 adreg4ch/l an5 adreg5dh/l an6 adreg6eh/l an7 adreg7fh/l an8 adreg08h/l an9 adreg19h/l an10 adreg2ah/l an11 adreg3bh/l an12 adreg4ch/l an13 adreg5dh/l an14 adreg6eh/l an15 adreg7fh/l an16 adreg08h/l an17 adreg19h/l an18 adreg2ah/l an19 adreg3bh/l an20 adreg4ch/l an21 adreg5dh/l an22 adreg6eh/l an23 adreg7fh/l a dreg08h/l a dreg7fh/l TMP1962C10BXBG 2006-02-21 tmp1962-363 16.2.8 data polling when the results of a/d conversion are processed by means of data polling without using interrupts, the eocf bit in the admod0 should be polled. if this flag is set, the specified a/d conversion result register pairs contain results. then, read those registers. to detect an overrun, first read the adregxh and then read the adregxl. if the ovrn is cleared to 0 and adrnrf is set to 1 in the adregxl, the register pair contains valid conversion results. TMP1962C10BXBG 2006-02-21 tmp1962-364 17. watchdog timer (wdt) the tmp1962 contains a watchdog timer (wdt). the wdt is used to regain control of the system in the event of software or system lockups due to spurious noises, etc. when a watchdog timer time-out occurs, the wdt generates a nonmaskable interrupt to the cpu. also, the time-out event can be programmed for system reset generation, which is accomplished by routing the time-out signal to the internal reset pin. 17.1 implementation figure 17.1 shows a block diagram of the wdt. figure 17.1 wdt block diagram internal reset wdmod TMP1962C10BXBG 2006-02-21 tmp1962-365 the wdt contains a 22-stage binary counter clocked by the f sys /2 clock. this binary counter provides 2 15 , 2 17 , 2 19 or 2 21 as a counter overflow signal, as programmed into the wdtp[1:0] field in the wdmod. when a counter overflow occurs, the wdt generates a wdt interrupt, as shown below. figure 17.2 default operation also, the counter overflow can be programmed to ca use a system reset as the time-out action. if so programmed, a counter overflow causes the wdt to assert the internal reset signal for a 22- to 29-state time. after a reset, the f sys clock is generated by dividing the high-speed oscillator clock (fc) by eight through the clock gear function (when the pll is used); the wdt clock source (f sys /2) is derived from this f sys clock. figure 17.3 reset operation 0 wdt interrupt wdt clear (via software) a write of a special clear-count code wdt counter n overflow overflow wdt counter n wdt interrupt 22-29 states (8.8~11.6 s @ f c = 40 mhz, f sys = 5 mhz, f sys/2 = 2.5 mhz) internal reset note: the tmp1962 continues sampling the plloff pin during a reset operation caused by the wdt. therefore, the plloff pin must be tied to either logic high or logic low. TMP1962C10BXBG 2006-02-21 tmp1962-366 17.2 register description the wdt is controlled by two registers called wdmod and wdcr. 17.2.1 watchdog timer mode register (wdmod) (1) time-out period (wdmod.wdtp[1:0]) this 2-bit field determines the duration of the wdt time-out interval. upon reset, the wdtp[1:0] field defaults to 00. figure 17.4 shows possible time-out periods. (2) wdt enable (wdmod.wdte) upon reset, the wdte bit is set to 1, enabling the wdt. to disable the wdt, the clearing of the wdte bit must be followed by a write of a speci al key code (b1h) to the wdcr register. this prevents a "lost" program from disabling the wdt operation. the wdt can be re-enabled simply by setting the wdte bit. (3) system reset (wdmod.rescr) this bit is used to program the wdt to generate a system reset on a time-out. upon reset, this bit is cleared; thus the time-out does not cause a system reset. 17.2.2 watchdog timer control register (wdcr) this register is used to disable the wd t and to clear the wdt binary counter. ? disabling the wdt the wdt can be disabled by clearing the wdmod.wdte to 0 and then writing the special disable code (b1h) to the wdcr register. wdmod 0 ? ? ? ? ? ? ? clears the wdte bit to 0. wdcr 1 0 1 1 0 0 0 1 writes the dis able code (b1h) to the wdcr. ? enabling the wdt the wdt can be enabled simply by setting the wdte bit in the wdmod to 1. ? clearing the wdt counter writing the special clear-count code (4eh) to the wdcr resets the binary counter to zero. the counting process begins again. wdcr 0 1 0 0 1 1 1 0 writes the clear-count code (4eh) to the wdcr. note: writing the disable code (bih) clears the binary counter. TMP1962C10BXBG 2006-02-21 tmp1962-367 7 6 5 4 3 2 1 0 bit symbol wdte wdtp1 wdtp0 i2wdt rescr ? read/write r/w r/w r/w r/w reset value 1 0 0 0 0 0 function wdt enable 1: enable time-out period 00: 2 16 /f sys 01: 2 18 /f sys 10: 2 20 /f sys 11: 2 22 /f sys idle 0: off 1: on 1: system reset by wdt must be written as 0. system reset 0 ? 1 internally routes the wdt time-out signal to the system reset watchdog timer time-out period wdmod TMP1962C10BXBG 2006-02-21 tmp1962-368 17.3 operation the watchdog timer is a kind of timer that generates an interrupt request if it times out. the wdt allows the user to program the time-out period in the wdtp[1:0 ] field in the wdmod register. while enabled, the software can reset the counter to zero at any time by wr iting a special clear-count code. if the software is unable to reset the counter before it reaches the time-out count, the wdt generates the intwd interrupt. in response to the interrupt, the cpu jumps to a system recovery ro utine to regain control of the system. the wdt can also output a time-out signal to a peripheral device so that the device can respond to the problem. the wdt begins counting immediately after reset. when the tmp1962 goes into stop mode, the wdt counter is reset to zero automatically and stops counting. the wdt continues counting while an off-chip peripheral has mastership of the bus (i.e., busak = 0). in idle mode, the i2wdt bit in the wdmod determin es whether or not to disable the wdt. the i2wdt bit can be programmed before putting the tmp1962 in idle mode. examples: (1) clearing the wdt binary counter 7 6 5 4 3 2 1 0 wdcr 0 1 0 0 1 1 1 0 writes the clear-count code (4eh) to the wdcr. (2) programming the time-out interval to 2 18 /f sys 7 6 5 4 3 2 1 0 wdmod 1 0 1 ? ? ? ? ? (3) disabling the watchdog timer 7 6 5 4 3 2 1 0 wdmod 0 ? ? ? ? ? ? ? clears the wdte bit to 0. wdcr 1 0 1 1 0 0 0 1 writes the di sable code (b1h) to the wdcr. TMP1962C10BXBG 2006-02-21 tmp1962-369 18. key-pressed wake-up 18.1 outline ? the tmp1962 has 14 key input channels (key0-keyd) that enable the pressing of a key to terminate stop mode or trigger an external interrupt. these 14 interrupts are, however, assumed as the same interrupt source (as specified in the cg block) when sent to the interrupt controller (intc). each key input can be enabled or disabled individually using the kwupstn register. ? the interrupt sensitivity and polarity (rising-edge trig gered, falling-edge triggered, high-level sensitive or low-level sensitive) can be specified individua lly for each key input using the kwupstn register. ? the interrupt service routine cl ears the key interrupt request through the kwupclr register. ? each key input pin has an internal pull-up resistor, which can be enabled or disabled by programming bit 0 (pe) of the kwupcnt. the settings of the pe and dpe bits apply to all 14 key inputs. 18.2 operation the tmp1962 has 14 key input pins (key0-keyd). the kwupen bit in the cg's imcgb1 register controls whether the key inputs are used to exit stop mode or used as general-purpose interrupt sources. when kwupen is set to 1, all of key0-keyd are used for stop wake-up signalin g. for each key input, the keynen bit in the kwupstn must be programmed to e ither enable or disable interrupts and the keyn[1:0] field in the same register must be programmed to specify signal sensitivity. the kwup circuit block detects key inputs and transmits the results to the imcgb1 regi ster in the cg, identifying the high level as an active state. the emcg[51:50] bits in the imcgb1 must be set to 01 (high-level sensitive). the cg in turn transmits the results to the intc, also identifying the high level as an active state. the intc must also be programmed so that the corresponding interrupt is high-level sensitive (01). when the kwupen bit in the imcgb1 register is cleared to 0 (default), all of key0 to keyd are used as general-purpose interrupts. in that case, the cg does not need to be programmed; only the intc must be programmed so that the interrupt is high-level sensitive. the kwupstn must also be programmed to en able interrupts and specify signal sensitivity. in the key interrupt service routine, writing 1010 to the kwupclr causes all key interrupt requests to be cleared. 18.3 pull-up resistors each key input pin has an internal pull-up resistor. wh en the kype bit in the kwup cnt is set to 1, pull-up resistors for all key input pins (key0-keyd) are enabled, except for the pins for which key input is disabled by clearing the keynen bit in the kwupstn. note: if another key input is detected before the interrupt service routine clears the interrupt request corresponding to the first key input, the routine clears all interrupt requests simultaneously. if another key input is detected after the interrupt service routine clears the interrupt re quest correspondi ng to the first key input, the new key input triggers another key interrupt. TMP1962C10BXBG 2006-02-21 tmp1962-370 (1) when using key input pins in static pull-up mode, the following procedures must be observed: ? initial setup after power-on 1) program the kwupcnt (kype = 1). 2) set the kwupstn.keynen bit to 1 for each key input to be used. 3) wait until the pull-up resistors are disabled. 4) specify an interrupt trigger in the kwupstn for each key input to be used. 5) clear the interrupt request with kwupclr. 6) program the cg and intc, as described in chapter 6, "interrupts." ? modifying an interrupt trigger for key inputs 1) disable key interrupts in the intc (imc1.il6[2:0] = 000). 2) modify an interrupt trigger in the kwupstn for each relevant key input. 3) clear the interrupt request with kwupclr. 4) enable key interrupts in the intc (program imc1.il6[2:0] as required). ? enabling additional key inputs 1) disable key interrupts in the intc (imc1.il6[2:0] = 000). 2) set the kwupstn.keynen bit to 1 for each key input to be used. 3) wait until the pull-up resistors are disabled. 4) specify an interrupt trigger in the kwupstn for each key input to be used. 5) clear the interrupt request with kwupclr. 6) enable key interrupts in the intc (program imc1.il6[2:0] as required). (2) when using key input pins in dynamic pull-up mode, the following procedures must be observed: ? initial setup after power-on 1) program the kwupcnt (kype = 1, tnsn = desired interval). 2) specify an interrupt trigger in the kwupstn for each key input to be used. 3) clear the interrupt request with kwupclr. 4) set the kwupstn.keynen bit to 1 for each key input to be used. 5) program the cg and intc, as described in chapter 6, "interrupts." ? modifying an interrupt trigger for key inputs 1) disable key interrupts in the intc (imc1.il6[2:0] = 000). 2) modify an interrupt trigger in the kwupstn for each relevant key input. 3) clear the interrupt request with kwupclr. 4) enable key interrupts in the intc (program imc1.il6[2:0] as required). ? en abling additional key inputs 1) disable key interrupts in the intc (imc1.il6[2:0] = 000). 2) specify an interrupt trigger in the kwupstn for each key input to be used. 3) clear the interrupt request with kwupclr. 4) set the kwupstn.keynen bit to 1 for each key input to be used. 5) enable key interrupts in the intc (program imc1.il6[2:0] as required). TMP1962C10BXBG 2006-02-21 tmp1962-371 (3) when using key input pins without enabling pull-up resistors, the following procedures must be observed: ? initial setup after power-on 1) program the kwupcnt (kype = 1). 2) specify an interrupt trigger in the kwupstn for each key input to be used. 3) clear the interrupt request with kwupclr. 4) set the kwupstn.keynen bit to 1 for each key input to be used. 5) program the cg and intc, as described in chapter 6, "interrupts." ? modifying an interrupt trigger for key inputs 1) disable key interrupts in the intc (imc1.il6[2:0] = 000). 2) modify an interrupt trigger in the kwupstn for each relevant key input. 3) clear the interrupt request with kwupclr. 4) enable key interrupts in the intc (program imc1.il6[2:0] as required). ? enabling additional key inputs 1) disable key interrupts in the intc (imc1.il6[2:0] = 000). 2) specify an interrupt trigger in the kwupstn for each key input to be used. 3) clear the interrupt request with kwupclr. 4) set the kwupstn.keynen bit to 1 for each key input to be used. 5) enable key interrupts in the intc (program imc1.il6[2:0] as required). key-pressed wake-up control register: kwupcnt 7 6 5 4 3 2 1 0 (0xffff_f372) bit symbol kype read/write r/w r/w reset value 0 0 0 0 0 0 0 function must be written as 0. must be set to 00. must be set to 00. must be set to 0. 0: disable pull-up 1: enable pull-up 18.4 key input detection timing (1) when pull-up registers are disabled (kype = 0) for each key input, the keyn[1:0] bits in the kwupstn register can specify one of four interrupt trigger types: high level, low level, rising edge and falling edge. the states of key inputs are always monitored. (2) when pull-up registers are enabled (kype = 1) for each key input, the keyn[1:0] bits in the kwupstn register can specify one of four interrupt trigger types: high level, low level, rising edge and falling edge. the states of key inputs are always monitored. 7 6 5 4 3 2 1 0 kwupst0 bit symbol key01 key00 key0en (0xffff_f363) read/write r/w r/w TMP1962C10BXBG 2006-02-21 tmp1962-372 reset value 1 0 0 function key0 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 0 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst1 bit symbol key11 key10 key1en (0xffff_f362) read/write r/w r/w reset value 1 0 0 function key1 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 1 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst bit symbol key21 key20 key2en (0xffff_f361) read/write r/w r/w reset value 1 0 0 function key2 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 2 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst3 bit symbol key31 key30 key3en (0xffff_f360) read/write r/w r/w reset value 1 0 0 function key3 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 3 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst4 bit symbol key41 key40 key4en (0xffff_f367) read/write r/w r/w reset value 1 0 0 function key4 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 4 interrupt input 0: disable 1: enable TMP1962C10BXBG 2006-02-21 tmp1962-373 7 6 5 4 3 2 1 0 kwupst5 bit symbol key51 key50 key5en (0xffff_f366) read/write r/w r/w reset value 1 0 0 function key5 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 5 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst6 bit symbol key61 key60 key6en (0xffff_f365) read/write r/w r/w reset value 1 0 0 function key6 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 6 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst7 bit symbol key71 key70 key7en (0xffff_f364) read/write r/w r/w reset value 1 0 0 function key7 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 7 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst8 bit symbol key81 key80 key8en (0xffff_f36b) read/write r/w r/w reset value 1 0 0 function key8 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 8 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst9 bit symbol key91 key90 key9en (0xffff_f36a) read/write r/w r/w reset value 1 0 0 function key9 interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y 9 interrupt input 0: disable 1: enable TMP1962C10BXBG 2006-02-21 tmp1962-374 7 6 5 4 3 2 1 0 kwupsta bit symbol keya1 keya0 keyaen (0xffff_f369) read/write r/w r/w reset value 1 0 0 function keya interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y a interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupstb bit symbol keyb1 keyb0 keyben (0xffff_f368) read/write r/w r/w reset value 1 0 0 function keyb interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y b interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupstc bit symbol keyc1 keyc0 keycen (0xffff_f36f) read/write r/w r/w reset value 1 0 0 function keyc interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y c interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupstd bit symbol keyd1 keyd0 keyden (0xffff_f36e) read/write r/w r/w reset value 1 0 0 function keyd interrupt trigger 00: low level 01: high level 10: falling level 11: rising level k e y d interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupclr bit symbol ke yclr3 keyclr2 keyclr1 keyclr0 (0xffff_f373) read/write w r e s e t v a l u e function ?1010? write of 00 clears all key interrupt requests TMP1962C10BXBG 2006-02-21 tmp1962-375 19. rom correction this chapter describes the rom correction function supported by the tmp1962. 19.1 features ? up to eight 8-word sequences of data can be replaced. ? when the address stored in an address register (addregn) matches the program counter (pc) value or the address generated by the dmac (the lower five b its of the address are "don't care"), the data at the specified address in the on-chip rom is replaced w ith the data from the ram area corresponding to the address register. ? writing an address to an address register causes rom correction for the address to be enabled automatically. ? a correction requiring the replacement of more than eight words can also be performed by replacing the rom data with an instruction code which makes a br anch to a specified location in the ram area which contains substitution data. 19.2 operation to correct data in a rom area (or a projected rom area), store the physi cal start address of the area in an address register (addreg0-addreg7 ). store the substitution data in the ram area corresponding to the address register. writing an address to an address regist er causes rom correction for the address to be enabled automatically. upon reset, the rom co rrection function is disabled. if the initial routine executed upon reset is used to correct rom data, write an addr ess to the relevant address register after a reset is released. the address registers to which addresses are written are enabled for rom correction. when the stored address matches the pc value (if the cpu has the bus right) or the source or destination address issued by the dmac (if the dmac has the bus right), the data at the specified address in the rom is replaced with the data stored in the corresponding ram ar ea. for example, storing addresses in the addreg0 and addreg3 enables correction for the respective rom areas, so that the rom correction circuit block constantly monitors the pc and dmac-issued addresses for a match with a specified address and, if a match is detected, replaces data, while ignoring the addreg2 and addreg4-addreg7. each address register has bits 31:5 although only bits 19:5 are used for address comparison, in order to simplify the circuit. a match detected in the rom correction circuit is internally anded with the ro mcs signal, which indicates a specified rom address block, to determine an exact match. rom addresses specified for correct ion must be located on eight-word boundaries, i.e., the lower five bits are 0. in other words, rom data is always replaced in 32-byte units. if only part of 32 bytes need to be replaced , substitution ram data corre sponding to the other bytes must be the same as the current data in the corresponding rom addresses. the following table shows the relationship be tween the address registers and ram areas. address register ram area addreg0 0xfffd_ff00 0xfffd_ff1f addreg1 0xfffd_ff20 0xfffd_ff3f addreg2 0xfffd_ff40 0xfffd_ff5f addreg3 0xfffd_ff60 0xfffd_ff7f addreg4 0xfffd_ff80 0xfffd_ff9f addreg5 0xfffd_ffa0 0xfffd_ffbf addreg6 0xfffd_ffc0 0xfffd_ffdf addreg7 0xfffd_ffe0 0xfffd_ffff TMP1962C10BXBG 2006-02-21 tmp1962-376 figure 19.1 rom correction block diagram address registers addregn compare circuit selector operand address instruction address rom selector operand data instruction data tx19 mpu gbif g-bus addregn write detection and hold circuit compare enable ram converter TMP1962C10BXBG 2006-02-21 tmp1962-377 19.3 registers (1) address registers 7 6 5 4 3 2 1 0 addreg0 bit symbol add07 add06 add05 (0xffff_e540) read/write r/w reset value 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol add015 add014 add013 add012 add011 add010 add09 add08 read/write r/w reset value 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol add023 add022 add021 add020 add019 add018 add017 add016 read/write r/w reset value 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol add031 add030 add029 add028 add027 add026 add025 add024 read/write r/w reset value 0 0 0 0 0 0 0 0 function 7 6 5 4 3 2 1 0 addreg1 bit symbol add17 add16 add15 (0xffff_e544) read/write r/w reset value 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol add115 add114 add113 add112 add111 add110 add19 add18 read/write r/w reset value 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol add123 add122 add121 add120 add119 add118 add117 add116 read/write r/w reset value 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol add131 add130 add129 add128 add127 add126 add125 add124 read/write r/w reset value 0 0 0 0 0 0 0 0 function TMP1962C10BXBG 2006-02-21 tmp1962-378 7 6 5 4 3 2 1 0 addreg2 bit symbol add27 add26 add25 (0xffff_e548) read/write r/w reset value 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol add215 add214 add213 add212 add211 add210 add29 add28 read/write r/w reset value 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol add223 add222 add221 add220 add219 add218 add217 add216 read/write r/w reset value 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol add231 add230 add229 add228 add227 add226 add225 add224 read/write r/w reset value 0 0 0 0 0 0 0 0 function 7 6 5 4 3 2 1 0 addreg3 bit symbol add37 add36 add35 (0xffff_e54c) read/write r/w reset value 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol add315 add314 add313 add312 add311 add310 add39 add38 read/write r/w reset value 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol add323 add322 add321 add320 add319 add318 add317 add316 read/write r/w reset value 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol add331 add330 add329 add328 add327 add326 add325 add324 read/write r/w reset value 0 0 0 0 0 0 0 0 function TMP1962C10BXBG 2006-02-21 tmp1962-379 7 6 5 4 3 2 1 0 addreg4 bit symbol add47 add46 add45 (0xffff_e550) read/write r/w reset value 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol add415 add414 add413 add412 add411 add410 add49 add48 read/write r/w reset value 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol add423 add422 add421 add420 add419 add418 add417 add416 read/write r/w reset value 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol add431 add430 add429 add428 add427 add426 add425 add424 read/write r/w reset value 0 0 0 0 0 0 0 0 function 7 6 5 4 3 2 1 0 addreg5 bit symbol add57 add56 add55 (0xffff_e554) read/write r/w reset value 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol add515 add514 add513 add512 add511 add510 add59 add58 read/write r/w reset value 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol add523 add522 add521 add520 add519 add518 add517 add516 read/write r/w reset value 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol add531 add530 add529 add528 add527 add526 add525 add524 read/write r/w reset value 0 0 0 0 0 0 0 0 function TMP1962C10BXBG 2006-02-21 tmp1962-380 7 6 5 4 3 2 1 0 addreg6 bit symbol add67 add66 add65 (0xffff_e558) read/write r/w reset value 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol add615 add614 add613 add612 add611 add610 add69 add68 read/write r/w reset value 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol add623 add622 add621 add620 add619 add618 add617 add616 read/write r/w reset value 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol add631 add630 add629 add628 add627 add626 add625 add624 read/write r/w reset value 0 0 0 0 0 0 0 0 function 7 6 5 4 3 2 1 0 addreg7 bit symbol add77 add76 add75 (0xffff_e55c) read/write r/w reset value 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol add715 add714 add713 add712 add711 add710 add79 add78 read/write r/w reset value 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol add723 add722 add721 add720 add719 add718 add717 add716 read/write r/w reset value 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol add731 add730 add729 add728 add727 add726 add725 add724 read/write r/w reset value 0 0 0 0 0 0 0 0 function note 1: dma transfer to an address register cannot be supported. dma transfer to a substitution data area in the ram is supported. the rom correction function is supported when either the cpu or dmac has an access right. note 2: writing the initial value 0x00 replaces the reset address. TMP1962C10BXBG 2006-02-21 tmp1962-381 20. dsu interface the dsu interface is used for software debugging using an external dsu-prob e unit. this serves as an interface to the dsu-probe, and cannot be used as a general-purpose port. consult the dsu-probe operation manual for a description of debugging using a dsu-probe. (1) security feature the TMP1962C10BXBG supports on-board debugging while it is installed on a printed circuit board. the TMP1962C10BXBG provides a secu rity feature to prevent debuggi ng. unsecuring the device enables debugging with a dsu-probe. (2) securing the device (disabling debugging with a dsu-probe) the device is secured in the initial state. debugging with a dsu-probe is disabled until the device is unsecured. (3) unsecuring the device (enabling debugging with a dsu-probe) the device may only be unsecured by clearing the seqon bit in the seqmod register and then writing a special code (0x0000_00c5) to the s ecurity control (seqcnt) register. this prevents runaway software from inadvertently turning off the security feature. however, a dsu-probe cannot read the contents of on-chip rom or write to registers other than the processor core, on-chip memory and external device. when the device is reset, the device is secured until it is unsecured. 31 30 29 28 27 26 25 24 seqmod bit symbol (0xffff_e510) read/write reset value function 23 22 21 20 19 18 17 16 bit symbol read/write reset value function 15 14 13 12 11 10 9 8 bit symbol read/write reset value function 7 6 5 4 3 2 1 0 bit symbol seqon read/write r/w reset value 1 function 1: security on 0: security off note: this register must be read as a 32-bit quantity. bits 1 to 31 are read as 0s. TMP1962C10BXBG 2006-02-21 tmp1962-382 31 30 29 28 27 26 25 24 seqcnt bit symbol (0xffff_e514) read/write w reset value function must be written as 0x0000_00c5. 23 22 21 20 19 18 17 16 bit symbol read/write w reset value function must be written as 0x0000_00c5. 15 14 13 12 11 10 9 8 bit symbol read/write w reset value function must be written as 0x0000_00c5. 7 6 5 4 3 2 1 0 bit symbol read/write w reset value function must be written as 0x0000_00c5. (4) application example the following flowchart exemplifies how to use the security feature with a dsu-probe. figure 20.1 using the security feature dsu-probe can be used until the chip is powered off. tmp1962 security on after a reset protect/unprotect judgement routine (user-created) turn off security feature? program seqmod and seqcnt to turn off security feature dsu-probe cannot be used. security remains on. yes no external port data, etc. note: this register must be read as a 32-bit quantity. TMP1962C10BXBG 2006-02-21 tmp1962-383 21. jtag interface the tmp1962 processor provides a boundary-scan interface that is compatible with joint test action group (jtag) specifications, using the industry-standard jtag protocol (ieee standard 1149.1/d6). this chapter describes that interface, including descriptio ns of boundary scanning, the pins and signals used by the interface, and the test access port (tap). 21.1 what boundary scanning is with the evolution of ever-denser integrated circuits (ics), surface-mounted devices, double-sided component mounting on printed-circuit boards (pcbs), and buried vias, in-circuit tests that depend upon making physical contact with internal board and chip connections have become more and more difficult to use. the greater complexity of ics has also meant that tests to fully exercise these chips have become much larger and more difficult to write. one solution to this difficulty has been the development of boundary-scan circuits. a boundary-scan circuit is a series of shift register cells placed between each pin and the internal circuitry of the ic to which the pin is connected, as shown in figure 21.1. no rmally, these boundary-scan cells are bypassed; when the ic enters test mode, however, the scan cells can be directed by the test program to pass data along the shift register path and perform various diagnostic tests. to accomplish this, the tests use the four signals described in the next section: tdi, tdo , tms , tck, and trst . figure 21.1 jtag boundary-scan cells integrated circuit c package pin boundary-scan cells TMP1962C10BXBG 2006-02-21 tmp1962-384 21.2 signal summary the jtag interface signals are listed below and shown in figure 21.2. ? tdi jtag serial data in ? tdo jtag serial data out ? tms jtag test mode select ? tck jtag serial clock input ? trst jtag test reset input figure 21.2 jtag interface signals and registers the jtag boundary-scan mechanism (re ferred to in this chapter as jtag mechanism ) allows testing of the connections between the processor, the printed circuit board to which it is attached, and the other components on the circuit board. the jtag mechanism does not provide any capability for testing the processor itself. 30 instruction register tap controller 0 bypass register 0 114 boundary-scan register jtdi pin jtd0 pin jtms pin jtck pin trst pin TMP1962C10BXBG 2006-02-21 tmp1962-385 21.3 jtag controller and registers the processor contains the following jtag controller and registers: ? instruction register ? boundary-scan register ? bypass register ? id code register ? test access port (tap) controller the processor executes the standard jtag extest operation associated with external test functionality testing. the basic operation of jtag is for the tap controller state machine to monitor the jtms input signal. when it occurs, the tap controller determines the test functionality to be implemented. this includes either loading the jtag instruction register (ir), or beginning a serial data scan through a data register (dr), listed in table 21.1. as the data is scanned in, the state of the jtms pin signals each new data word, and indicates the end of the data stream. the data register to be selected is determined by the contents of the instruction register. 21.3.1 instruction register the jtag instruction register includes eight shift register-based cells; this register is used to select the test to be performed and/or the test data register to be accessed. as listed in table 21.1, this encoding selects either the boundary-scan register or the bypass register or device identification register. table 21.1 jtag instruction register bit encoding instruction code (msb lsb) instruction selected data register 0000 extest boundary scan register 0001 sample/preload boundary scan register 0010 to 1110 reserved reserved 1111 bypass bypass register figure 21.3 shows the format of the instruction register 3 2 1 0 msb lsb figure 21.3 instruction register the instruction code is shifted out to the instruction register from the lsb. figure 21.4 instruction register shift direction lsb tdo tdi msb TMP1962C10BXBG 2006-02-21 tmp1962-386 21.3.2 bypass register the bypass register is 1 bit wide. when the tap controller is in the shift-dr (bypass) state, the data on the tdi pin is shifted into the bypass register, and the bypass register output shifts to the tdo output pin. in essence, the bypass register is a short-circuit which allows bypassing of board-level devices, in the serial boundary-scan chain, whic h are not required for a specific test. the logical location of the bypass register in the boundary-scan chain is shown in figure 21.5. use of the bypass register speeds up access to boundary-scan registers in those ics that rema in active in the board-level test datapath. figure 21.5 bypass register operation 21.3.3 boundary-scan register the boundary scan register includes all of the inputs and outputs of the tmp1962 processor, except some analog output and control signals. the pins of the tmp1962 chip can be configured to drive any arbitrary pattern by scanning into the boundary scan register from the shift-dr state. incoming data to the processor is examined by shifting while in the capture-dr state with the boundary scan register enabled. the boundary-scan register is a single, 115-bit-wide, sh ift register-based path containing cells connected to all input and output pads on the tmp1962 processor. the tdi input is loaded to the lsb of the bound ary scan register. the msb of the boundary scan register is retrieved from the jtdo output. jtdo board input ic package board jtdi bypass register boundary-scan register pad cell board output jtdi jtdi jtdo jtdo jtdo jtdi jtdo jtdi TMP1962C10BXBG 2006-02-21 tmp1962-387 21.3.4 test access port (tap) the test access port (tap) consists of the five signal pins: trst , tdi, tdo , tms , and tck . serial test data and instructions are communicated over these five signal pins, along with control of the test to be executed. as figure 21.6 shows, data is serially scanned into one of the three registers ( instruction register, bypass register, or the boundary-scan register) from the tdi pin, or it is scanned from one of these three registers onto the tdo pin. the tms input controls the state transitions of the main tap controller state machine. the tck input is a dedicated test clock that allows serial jtag data to be shifted synchronously, independent of any chip-specific or system clocks. figure 21.6 jtag test access port data on the tdi and tms pins is sampled on the rising edge of the tck input clock signal. data on the tdo pin changes on the falling edge of the tck clock signal. 21.3.5 tap controller the processor implements the 16-state tap controller as defined in the ieee jtac specification. 21.3.6 controller reset the tap controller state machine can be put into reset state the following: ? assertion of the trst signal (low) resets the tap controller. ? keeping the tms input signal asserted through five consecutive rising edges of tck input. in either case, keeping tms asserted maintains the reset state. tck data scanned out serially tdo sampled on falling edge of tck tms and tdi sampled on rising edge of tck data scanned in serially tdi pin tms pin tdo pin 0 0 3 instruction register bypass register 115 boundary-scan registe 0 0 0 3 instruction register bypass register 115 boundary-scan register 0 TMP1962C10BXBG 2006-02-21 tmp1962-388 21.3.7 tap controller the state transition diagram of the ta p controller is shown in figure 21 .7. each arrow between states is labeled with a 1 or 0, indicating the logic value of tms that must be set up before the rising edge of tck to cause the transition. test-logic-reset 1 0 0 1 0 1 run-test/idle select-dr-scan 1 1 capture-dr 0 shift-dr 1 exit 1-dr 0 pause-dr 1 exit 2-dr 1 update-dr 0 1 0 0 1 select-ir-scan capture-ir 0 shift-ir 1 exit 1-ir 0 pause-ir 1 exit 2-ir 1 update-ir 0 1 1 00 1 0 0 0 figure 21.7 tap controller state diagram the following paragraphs describe each of the controller states. the left vertical column in figure 21.7 is the data column, and the right vertical column is the instruction column. the data column and instruction column reference data register (dr) and instruction register (ir), respectively. TMP1962C10BXBG 2006-02-21 tmp1962-389 ? test-logic-reset when the tap controller is in the reset state, th e device identification register is selected as default. the three most significant bits of the bo undary-scan register are cleared to 0, disabling the outputs. the controller remains in this state while tms is high. if tms is held low while the controller is in this state, then the controller moves to the run-test/idle state. ? run-test/idle in the run-test/idle state, the ic is put in a test mode only when certain instructions such as a built-in self test (bist) instruc tion are present. for instructions that do not cause any activities in this state, all test data registers selected by the current instruction retain their previous states. the controller remains in this state while tms is held low. when tms is high, the controller moves to the select-dr-scan state. ? select-dr-scan this is a temporary controller state. here, the ic does not execute any specific functions. if tms is held low when the controller is in this state, then the controller moves to the capture-dr state. if tms is held high, the c ontroller moves to the select-ir-scan state in the instruction column. ? select-ir-scan this is a temporary controller state. here, the ic does not execute any specific functions. if tms is held low when the controller is in this state, then the controller moves to the capture-ir state. if tms is held high, the controller returns to the test-logic-reset state. ? capture-dr in this controller state, if the test data register selected by the current instruction on the rising edge of tck has parallel inputs, then data can be parallel-loaded into the shift portion of the data register. if the test data register does not have parallel inputs, or if data need not be loaded into the selected data register, then the data register retains its previous state. if tms is held low while the controller is in this state, the controller moves to the shift-dr state. if tms is held high, the controller moves to the exit1-dr state. ? shift-dr in this controller state, the test data regist er connected between tdi and tdo shifts data one stage forward towards its serial output. when the controller is in this state, then it remain s in the shift-dr state if tms is held low, or moves to the exit1-dr state if tms is held high. TMP1962C10BXBG 2006-02-21 tmp1962-390 ? exit 1-dr this is a temporary controller state. if tms is held low when the controller is in th is state, the controller moves to the pause-dr state. if tms is held high, the cont roller moves to the update-dr state. ? pause-dr this state allows the shifting of the data regist er selected by the instru ction register to be temporarily suspended. both the instruction register and the data register retain their current states. when the controller is in this state, then it remain s in the pause-dr state if tms is held low, or moves to the exit2-dr state if tms is held high. ? exit 2-dr this is a temporary controller state. when the controller is in this state, then it return s to the shift-dr state if tms is held low, or moves on to the update-dr state if tms is held high. ? update-dr in this state, data is latched, on the falling edge of tck, onto the parallel outputs of the data registers from the shift register path. the data held at the parallel output does not change while data is shifted in the associated shift register path. when the controller is in this state, it moves to either the run-test/idle state if tms is held low, or the select-dr-scan stat e if tms is held high. ? capture-ir in this state, data is parallel-loaded into the in struction register. the two least significant bits are assigned the values ?01?. the higher-order bits of the instruction register can receive any design specific values. the capture-ir state is used for testing the instruction register. faults in the instruction register, if any exist, may be detected by shifting out the data loaded in it. when the controller is in this state, it moves to either the shift-ir state if tms is low, or the exit1-ir state if tms is high. ? shift-ir in this state, the instruction register is conne cted between tdi and tdo and shifts the captured data toward its serial output on the rising edge of tck. when the controller is in this state, it remains in the shift-ir state if tms is low, or moves to the exit1-ir state if tms is high. TMP1962C10BXBG 2006-02-21 tmp1962-391 ? exit 1-ir this is a temporary controller state. when the controller is in this state, it moves to e ither the pause-ir state if tms is held low, or the update-ir state if tms is held high. ? pause-ir this state allows the shifting of the instruction register to be temporarily suspended. both the instruction register and the data re gister retain their current states. when the controller is in this state, it remains in the pause-ir state if tms is held low, or moves to the exit2-ir state if tms is held high. ? exit 2-ir this is a temporary controller state. when the controller is in this state, it moves to either the shift-ir state if tms is held low, or the update-ir state if tms is held high. ? update-ir this state allows the instruction previously shifted into the instruction register to be output in parallel on the rising edge of tck. then it becomes the current instruction, setting a new operational mode. when the controller is in this state, it moves to either the run-test/idle state if tms is low, or the select-dr-scan state if tms is high. TMP1962C10BXBG 2006-02-21 tmp1962-392 table 21.2 shows the boundary scan order of the processor signals. table 21.2 tmp1962 jtag boundary-scan ordering [tdi] 1: pj4 2: pj2 3: pcst3 4: psct0 5: pj3 6: sdi/ dint 7: pcst2 8: sdao/tpc 9: bw0 10: dbge 11: dclk 12: pj0 13: pcst1 14: sysrdy 15: pj1 16: dreset 17: test5 18: reset 19: plloff 20: nmi 21: bw1 22: pn7 23: pn2 24: pn6 25: pn5 26: pn3 27: pn4 28: pn1 29: po5 30: pn0 31: po6 32: po3 33: po2 34: po1 35: pp6 36: po0 37: pp5 38: pp7 39: po4 40: pp3 41: pp1 42: pp2 43: po7 44: pp4 45: pp0 46: pb2 47: pb3 48: pb7 49: pb0 50: pb1 51: pb6 52: pb4 53: pa1 54: pa4 55: pf3 56: pa7 57: pa3 58: pa0 59: pf4 60: pa2 61: pb5 62: pg5 63: pa6 64: pa5 65: pf7 66: pf2 67: pf1 68: pf0 69: pg7 70: pf6 71: pg0 72: pf5 73: pd7 74: pg3 75: pg1 76: pg4 77: pg2 78: pd6 79: pd3 80: pd1 81: pd2 82: pg6 83: pd5 84: pd0 85: pd4 86: pc2 87: pc6 88: pc1 89: pc0 90: pc7 91: ph1 92: pc3 93: ph0 94: pc4 95: ph5 96: ph4 97: ph3 98: ph2 99: pc5 100: pe2 101: pe0 102: pe1 103: ph7 104: ph6 105: pe5 106: pe3 107: pe4 108: rstpup 109: pe6 110: pe7 111: p53 112: p60 113: p57 114: p50 115: p52 116: p64 117: p63 118: p56 119: p67 120: p62 121: p66 122: p55 123: p51 124: p26 125: p65 126: p20 127: p54 128: p61 129: p21 130: p22 131: p02 132: p23 133: p25 134: p24 135: p00 136: p27 137: p01 138: p06 139: p03 140: p05 141: p04 142: p11 143: p10 144: p07 145: p12 146: p15 147: p13 148: p14 149: p36 150: p17 151: p34 152: p40 153: p32 154: p33 155: p30 156: p16 157: p41 158: p35 159: p44 160: p37 161: p31 162: p43 163: p42 164: pk5 165: pi7 166: pi6 167: pk7 168: pi5 169: pi4 170: pi3 171: pm7 172: pk6 173: pi1 174: pi2 175: pi0 176: pk3 177: pk1 178: pk4 179: pk2 180: pl7 181: pm5 182: pk0 183: pm4 184: pm6 185: pm3 186: pm0 187: pm1 188: pm2 189: pl6 190: pl2 191: pl5 192: pl4 193: pl0 194: pl3 195: pl1 196: p75 197: p74 198: p77 199: p73 200: p70 201: p71 202: p72 203: p86 204: p84 205: p83 206: p85 207: p76 208: p82 209: p80 210: p81 211: p87 212: p97 213: p93 214: p94 215: p96 216: p90 217: p95 218: p91 219: p92 [tdo]: TMP1962C10BXBG 2006-02-21 tmp1962-393 21.4 instructions for jtag this section defines the instructions supplied and the oper ations that occur in response to those instructions. 21.4.1 the extest instruction this instruction is used for external interconnect test, and targets the boundary scan register between tdi and tdo. the extest instruction permits bsr cells at output pins to shift out test patterns in the update-dr state and those at input pins to capture test results in the capture-dr state. typically, before extest is executed, the initializati on pattern is first shifted into the boundary scan register using the sample/preload instruction. in the update-dr state, the boundary scan register loaded with the initialization pattern causes known data to be driven immediately from the ic onto its external interconnects. this eliminates the possibility of bus conflicts damaging the ic outputs. the flow of data through the boundary scan register while the extest instruction is selected is shown in figure 21.8, which follows: figure 21.8 test data flow while the extest instruction is selected the following steps describe the basic test algorithm of an external interconnect test. 1. initialize the tap controller to the test-logic-reset state. 2. load the instruction register with sample/preload. this causes the boundary scan register to be connected between tdi and tdo. 3. initialize the boundary scan register by shifting in determinate data. 4. then, load the initial test data into the boundary scan register. 5. load the instruction register with extest. 6. capture the data applied to the input pin into the boundary scan register. 7. shift out the captured data while simultaneously shifting in the next test pattern. 8. read out the data in the boundary scan register onto the output pin. steps 6 to 8 are repeated for each test pattern. core logic output tdo input tdi boundary scan path TMP1962C10BXBG 2006-02-21 tmp1962-394 21.4.2 the sample/preload instruction this instruction targets the boundar y scan register between tdi and tdo. as the instruction's name implies, two functions are performed through use of the sample/ preload instruction. ? sample allows the input and output pads of an ic to be monitored. while it does so, it does not disconnect the system logic from the ic pins. the sample function occurs in the capture-dr controller state. an example application of sample is to take a snapshot of the activity of the ic's i/o pins so as to verify the interaction between ics during normal functional operation. the flow of data for the sample phase of the sample/prelo ad instruction is shown in figure 21.9. figure 21.9 test data flow while sample is selected ? preload allows the boundary scan register to be initialized before another instruction is selected. for example, prior to selection of the extest instruction, initialization data is shifted into the boundary scan register using preload as described in the previous subsection. preload permits shifting of the boundary scan register without interfering with the normal operation of the system logic. the flow of data for the preloa d phase of the sample/preload instruction is shown in figure 21.10. figure 21.10 test data flow while preload is selected output tdo input tdi boundary scan path core logic core logic output tdo input tdi boundary scan path TMP1962C10BXBG 2006-02-21 tmp1962-395 21.4.3 the bypass instruction this instruction targets the bypass register betwee n jtdi and jtdo. the bypass register provides a minimum length serial path through the ic (or between jtdi and jtdo) when the ic is not required for the current test. the bypass instruction does not cause interference to the normal operation of the on-chip system logic. the flow of data through the bypass register while the bypass instruction is selected is shown in figure 21.11. figure 21.11 test data flow while the bypass instruction is selected 21.5 note this section describes details of jtag boundary-scan operation that are specific to the processor. ? the x2 , and x1 signal pads do not support jtag. ? when performing a jtag operation, be sure to run the masterclock before and after a reset operation to properly release the processor reset. ? reset for jtag (1) jtag circuit is initialized by trst assertion. and then deassert trst . (2) at input to tms = 1 and asserted for more 5 tck cycles. tdo tdi bypass register 1-bit TMP1962C10BXBG 2006-02-21 tmp1962-396 22. electrical characteristics the letter x in equations presented in this chapter re presents the cycle period of the fsys clock selected through the programming of the syscr1.sysck bit. the fsys clock may be derived from either the high-speed or low-speed crystal oscillator. the programmi ng of the clock gear function also affects the fsys frequency. all relevant values in this chapter are calculated with the high-speed (fc) system clock (syscr1.sysck = 0) and a clock gear factor of 1/fc (syscr1.gear[1:0] = 00). 22.1 absolute maximum ratings parameter symbol rating unit v cc15 (core) ? 0.3 to 3.0 v cc2 (i/o) ? 0.3 to 4.0 v cc3 (i/o) ? 0.3 to 4.0 supply voltage avcc (a/d) ? 0.3 to 3.6 v input voltage v in ? 0.3 to v cc + 0.3 v per pin i ol 5 low-level output current total i ol 50 per pin i oh ? 5 high-level output current total i oh 50 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) t solder 260 c storage temperature t stg ? 65 to 150 c operating temperature t opr ? 20 to 85 c v cc15 = dvcc15 = cvcc15, v cc 2 = dvcc2, v cc 3 = dvcc3n (n = 1 to 4), avcc = avcc3m (m = 1 to 2), v ss = dvss* = avss* = cvss note: absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. the equipment manufacturer should design so that no absolute maximum ratings value is exceeded with respect to current, voltage, power dissipation, temperature, etc. exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to ic blowup and/or burning. TMP1962C10BXBG 2006-02-21 tmp1962-397 22.2 dc electrical characteristics (1/4) ta = ?20 to 85c parameter symbol conditions min typ (note 1) max unit dvcc15 fosc = 10 to 13.5 mhz fsys = 3.75 to 40.5 mhz pllon, intlv = ?h? 1.35 1.65 dvcc2 fsys = 3 to 40.5 mhz 2.3 3.3 supply voltage cvcc15 = dvcc15 cvss = dvss = 0 v dvcc3n (n = 1 to 4) fsys = 3 to 40.5 mhz 1.65 3.3 v 2.7 v avcc32 avcc31 3.3 v p7-p9 (used as a port) v il1 1.65 avcc32 avcc31 < 2.7 v 0.3 avcc31 0.3 avcc32 1.65 v dvcc3n 3.3 v (n = 1 to 4) p0-p6, pa-pc, pd0-pd6, pe0-pe2, pf2-pf7, pg-ph, pi7, pj1-pj4, pl-pp v il2 2.3 v dvcc2 3.3 v 0.3 dvcc3n 0.3 dvcc2 2.7 v dvcc3n 3.3 v (n = 1 to 4) 2.7 v dvcc2 3.3 v 0.15 dvcc3n pd7, pe3-pe7, pf0-pf1, pi0-pi6, pj0, pk, plloff , rstpup, reset dreset , dbge sdi/ dint , tck, tms, tdi, trst nmi , bw0, bw1 v il3 1.65 v dvcc3n < 2.7 v (n = 1 to 4) 2.3 v dvcc2 < 2.7 v 0.1 dvcc3n 0.1 dvcc2 low-level input voltage x1 v il4 1.35 v cvcc15 1.65 v ? 0.3 0.1 cvcc15 v note 1: ta = 25c, dvcc3 = 3.0 v, dvcc2 = 2. 5 v, avcc3 = 3.3 v, unless otherwise noted. TMP1962C10BXBG 2006-02-21 tmp1962-398 22.3 dc electrical characteristics (2/4) ta = ?20 to 85c parameter symbol conditions min typ. (note 1) max unit 2.7 v avcc32 avcc31 3.3 v p7-p9 (used as a port) v ih1 1.65 avcc32 avcc31 < 2.7 v 0.7 avcc31 0.7 avcc32 1.65 v dvcc3n 3.3 v (n = 1 to 4) 0.7 dvcc3n p0-p6, pa-pc, pd0-pd6, pe0-pe2, pf2-pf7, pg-ph, pi7, pj1-pj4, pl-pp v ih2 2.3 v dvcc2 3.3 v 0.7 dvcc2 2.7 v dvcc3n 3.3 v (n = 1 to 4) 2.7 v dvcc2 3.3 v 0.85 dvcc3n pd7, pe3-pe7, pf0-pf1, pi0-pi6, pj0, pk, plloff , rstpup, reset dreset , dbge sdi/ dint , tck, tms, tdi, trst nmi , bw0, bw1 v ih3 1.65 v dvcc3n < 2.7 v (n = 1 to 4) 2.3 v dvcc2 < 2.7 v 0.9 dvcc3n 0.9 dvcc2 high-level input voltage x1 v ih4 1.35 v cvcc15 1.65 v 0.9 cvcc15 dvcc3n + 0.3 dvcc2 + 0.3 cvcc15 + 0.2 v i ol = 2 ma dvcc3n 2.7 v dvcc2 2.7 v 0.4 low-level output voltage v ol i ol = 500 a dvcc3n < 2.7 v dvcc2 < 2.7 v 0.2 dvcc3n 0.4 0.2 dvcc2 0.4 i oh = ? 2 ma dvcc3n 2.7 v dvcc2 2.7 v 2.4 high-level output voltage v oh i oh = ? 500 a dvcc3n < 2.7 v dvcc2 < 2.7 v 0.8 dvcc3n 0.8 dvcc2 v note 1: ta = 25c, dvcc3 = 3.0 v, dvcc2 = 2. 5 v, avcc3 = 3.3 v, unless otherwise noted. TMP1962C10BXBG 2006-02-21 tmp1962-399 22.4 dc electrical characteristics (3/4) ta = ?20 to 85c parameter symbol conditions min typ. (note 1) max unit input leakage current i li 0.0 v in dvcc2 0.0 v in dvcc3n (n = 1 to 4) 0.0 v in avcc31 0.0 v in avcc32 0.02 5 output leakage current i lo 0.2 v in dvcc2 ? 0.2 0.2 v in dvcc3n ? 0.2 (n = 1 to 4) 0.2 v in avcc31 ? 0.2 0.2 v in avcc32 ? 0.2 0.05 10 a v stop (dvcc15) 1.35 1.65 v stop1 (dvcc2) v il2 = 0.2dvcc2, v il3 = 0.1dvcc2 v ih2 = 0.8dvcc2, v ih3 = 0.9dvcc2 2.3 3.3 power-down voltage (stop mode ram backup) v stop2 (dvcc3) (avcc3) v il = 0.3dvcc33, v il1 = 0.3avcc31,32 v il2 = 0.3dvcc3n, v il3 = 0.1dvcc3n v ih = 0.7dvcc33, v ih1 = 0.7avcc31,32 v ih2 = 0.7dvcc3n, v ih3 = 0.9dvcc3n (n = 1 to 4) 1.65 3.3 v pull-up resistor at reset rrst dvcc2 = 2.5 v 0.2 v 20 50 240 k ? 2.7 v dvcc3n 3.3 v (n = 2, 4) 2.7 v dvcc2 3.3 v 0.4 0.9 schmitt width pd7, pe3-pe7, pf0-pf1, pi0-pi6, pj0, pk, plloff , rstpup, reset , dreset , dbge , sdi/ dint , tck, tms, tdi, trst , nmi , bw0, bw1 vth 1.65 v dvcc3n < 2.7 v (n = 2, 4) 2.3 v dvcc2 < 2.7 v 0.3 0.6 v dvcc3n = 3.0 v 0.3 v (n = 2 to 4) 15 50 100 dvcc3n = 2.5 v 0.2 v (n = 2 to 4) dvcc2 = 2.5 v 0.2 v 20 50 240 programmable pull-up/ pull-down resistor p32-p37,p40-p43 key0-keyd, dreset, dbge , sdi/ dint , tck, tms, tdi, trst pkh dvcc3n = 2.0 v 0.2 v (n = 2 to 4) dvcc2 = 2.0 v 0.2 v 25 160 600 k ? pin capacitance (except power supply pins) c io fc = 1 mhz 10 pf note 1: ta = 25c, dvcc3n = 3.0 v, dvcc2 = 2.5 v, avcc3 = 3.0 v, unless otherwise noted. TMP1962C10BXBG 2006-02-21 tmp1962-400 22.5 dc electrical characteristics (4/4) dvcc15 = cvcc15 = 1.5 v 0.15 v, dvcc2 = 2.5 v 0.2 v, dvcc3n = 3.0 v 0.3 v, avcc3m = 3.3 v 0.2 v ta = 20 to 85c (n = 1 to 4, m = 1, 2) parameter symbol conditions min typ. (note 1) max unit normal (note 2): gear = 1/1 38 46 idle (doze) 16 28 idle (halt) f sys = 40.5 mhz (f osc = 13.5 mhz, pllon) intlv = ?h? 13 23 ma stop i cc dvcc15 = cvcc15 = 1.35 to 1.65 v dvcc2 = 2.3 to 2.7 v dvcc3n = 1.65 to 3.3 v avcc3m = 3.7 to 3.3 v 50 900 a note 1: ta = 25c, dvcc15 = 1.5 v, dvcc2 = 2.5 v, dvcc3n = 3.0 v, avcc3m = 3.0 v, unless otherwise noted. note 2: measured with the cpu dr ystone operating, all i/o peripher als channel on, and 16-bit external bus operated with 4 system clocks. note 3: the supply current flowing through the dv cc15, dvcc2, dvcc3n, cvcc15 and avcc3m pins is included in the digital supply current parameter (icc). TMP1962C10BXBG 2006-02-21 tmp1962-401 22.6 10-bit adc electrical characteristics dvcc15 = cvcc15 = 1.5 0.15 v, dvcc2 = 2.5 0.2 v, dvcc3n = 3.0 0.3 v, avcc3m = 3.0 0.3 v, avss = dvss, ta = ? 20 to 85c parameter symbol conditions min typ. (note 1) max unit 2.7 3.3 analog reference voltage ( + ) vrefh avccm ? 0.3 avcc avccm + 0.3 v analog reference voltage ( ? ) vrefl avss avss avss + 0.2 v analog input voltage vain vrefl vrefh v a/d conversion avccm = vrefh = 3.0 v 0.3 v dvss = avss = vrefl 0.35 1.0 ma analog supply current non-a/d conversion iref avccm = vrefh = 3.0 v 0.3 v dvss = avss = vrefl 0.02 10 a analog input capacitance ? 5.0 pf analog input impedance ? 5.0 k ? inl error ? 2 3 lsb dnl error ? 1.5 3 lsb offset error ? 2 3 lsb gain error ? avccm = vrefh = 3.0 v 0.3 v dvss = avss = vrefl ain resistance < 13.3 k ? ain load capacitance < 20 pf avccm load capacitance 10 f vrefh load capacitance 10 f conversion time 7.9 s note* 2 6 lsb note 1: 1lsb = (vrefh ? vrefl)/1024[v] note 2: the supply current flowing through the avcc m pin is included in the digital supply current parameter (icc). " 7 4 4 " * / note*:connection of an external capacitor is recommended* 0.1 f TMP1962C10BXBG 2006-02-21 tmp1962-402 ac electrical characteristics 22.6.1 multiplex bus mode (1) dvcc15 = cvcc15 = 1.5 v 0.15 v, dvcc2 = 2.5 v 0.2 v, avcc3m = 3.0 0.3 v, dvcc33 = 3.0 v 0.3 v, ta = ? 20 to 85 c 1. ale width = 0.5 clock cycle, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 0.5x ? 4.3 8 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 0.5x ? 0.3 12 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.3 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl x ? 5.1 19.5 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach x ? 5.1 19.5 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + w) ? 35.8 38 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + w) ? 35.8 38 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 30.7 18.5 ns 13 rd width low t rr x (1 + w) ? 2.7 46.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 3.2 46 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 4.2 45 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (3 + 0.5) ? 21.6 64.5 ns 20 a0-a15 valid to wait input t awl x (3 + 0.5) ? 21.6 64.5 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 4.1 x (1.5 + 3 + n ? 2) ? 18.7 57.4 67.4 ns note: nos. 1 to 18 indicate the values obtained with 1 programmed wait state. nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion TMP1962C10BXBG 2006-02-21 tmp1962-403 2. ale width = 1.5 clock cycl es, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 1.5x ? 3.9 33 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 1.5x ? 0.4 36.5 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.4 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 5.2 44 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 5.2 44 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (3 + w) ? 35.9 62.5 ns 11 a16-a23 valid to d0-d15 data in t adh x (3 + w) ? 35.9 62.5 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 30.7 18.5 ns 13 rd width low t rr x (1 + w) ? 2.7 46.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x 24.6 ns 16 wr or hwr width low t ww x (1 + w) ? 3.2 46 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 4.2 45 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (4 + 0.5) ? 21.7 89 ns 20 a0-a15 valid to wait input t awl x (4 + 0.5) ? 21.7 89 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 4.1 x (1.5 + 3 + n ? 2) ? 18.7 57.4 67.4 ns note: nos. 1 to 18 indicate the values obtained with 1 programmed wait state. nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion TMP1962C10BXBG 2006-02-21 tmp1962-404 (2) dvcc15 = cvcc15 = 1.5 v 0.15 v, dvcc2 = 2.5 v 0.2 v, avcc3m = 3.3 0.2 v, dvcc33 = 2.5 v 0.2 v, ta = ? 20 to 85 c 1. ale width = 0.5 clock cycle, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 0.5x ? 2.3 10 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 0.5x ? 0.3 12 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.3 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl x ? 5.1 19.5 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach x ? 5.1 19.5 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + w) ? 36.8 37 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + w) ? 36.8 37 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 31.7 17.5 ns 13 rd width low t rr x (1 + w) ? 2.2 47 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 2.7 46.5 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 45.5 ns 18 d0-d15 hold after wr or hwr negated t wd x ?0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (3 + 0.5) ? 22.6 63.5 ns 20 a0-a15 valid to wait input t awl x (3 + 0.5) ? 22.6 63.5 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 5.1 x (1.5 + 3 + n ? 2) ? 19.7 56.4 66.4 ns note: nos. 1 to 18 indicate the values obtained with 1 programmed wait state. nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion TMP1962C10BXBG 2006-02-21 tmp1962-405 2. ale width = 1.5 clock cycl es, 1 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 1.5x ? 2.4 34.5 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 1.5x ? 0.4 36.5 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.4 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 5.2 44 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 5.2 44 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (3 + w) ? 36.9 61.5 ns 11 a16-a23 valid to d0-d15 data in t adh x (3 + w) ? 36.9 61.5 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 31.7 17.5 ns 13 rd width low t rr x (1 + w) ? 2.2 47 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 2.7 46.5 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 45.5 ns 18 d0-d15 hold after wr or hwr negated t wd x ?0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (4 + 0.5) ? 22.6 88.1 ns 20 a0-a15 valid to wait input t awl x (4 + 0.5) ? 22.6 88.1 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 5.1 x (1.5 + 3 + n ? 2) ? 19.7 56.4 66.4 ns note: nos. 1 to 18 indicate the values obtained with 1 programmed wait state. nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion TMP1962C10BXBG 2006-02-21 tmp1962-406 (3) dvcc15 = cvcc15 = 1.5 v 0.15 v, dvcc2 = 2.5 v 0.2 v, avcc3m = 3.3 0.2 v, dvcc33 = 1.8 v 0.15 v, ta = ? 20 to 85 c 1. ale width = 0.5 clock cycle, 2 programmed wait state equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 33333 ns 2 a0-a15 valid to ale low t al 0.5x ? 2.3 10 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 0.5x ? 0.3 12 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.3 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl x ? 5.1 19.5 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach x ? 5.1 19.5 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + w) ? 42.4 56 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + w) ? 42.4 56 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 37.3 36.5 ns 13 rd width low t rr x (1 + w) ? 2.3 71.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 2.8 71 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 70 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (3 + 0.5) ? 28.1 58 ns 20 a0-a15 valid to wait input t awl x (3 + 0.5) ? 28.1 58 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 2) ? 6.1 x (1.5 + 3 + n ? 2) ? 24.7 55.4 61.4 ns note: nos. 1 to 18 indicate the values obtained with 1 programmed wait state. nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion TMP1962C10BXBG 2006-02-21 tmp1962-407 2. ale width = 1.5 clock cycl es, 2 programmed wait states equation 40.5 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 24.6 ns 2 a0-a15 valid to ale low t al 1.5x ? 2.4 34.5 ns 3 a0-a15 hold after ale low t la 0.5x ? 1.8 10.5 ns 4 ale pulse width high t ll 1.5x ? 0.4 36.5 ns 5 ale low to rd , wr or hwr asserted t lc 0.5x ? 2.3 10 ns 6 rd , wr or hwr negated to ale high t cl x ? 0.6 24 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 5.2 44 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 5.2 44 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 1.6 23 ns 10 a0-a15 valid to d0-d15 data in t adl x (3 + w) ? 42.5 80.5 ns 11 a16-a23 valid to d0-d15 data in t adh x (3 + w) ? 42.5 80.5 ns 12 rd asserted to d0-d15 data in t rd x (1 + w) ? 37.3 36.5 ns 13 rd width low t rr x (1 + w) ? 2.3 71.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 0.1 24.5 ns 16 wr or hwr width low t ww x (1 + w) ? 2.8 71 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + w) ? 3.8 70 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 0.1 24.5 ns 19 a16-a23 valid to wait input t awh x (4 + 0.5) ? 28.1 82.6 ns 20 a0-a15 valid to wait input t awl x (4 + 0.5) ? 28.1 82.6 ns 21 wait hold after rd , wr or hwr asserted t cw x (0.5 + 3 + n ? 1) ? 6.1 x (1.5 + 3 + n ? 1) ? 24.7 80 86 ns note: nos. 1 to 18 indicate the values obtained with 1 programmed wait state. nos. 19 and 20 indicate the values obtained with 4 externally generated wait states with n = 1. ac measurement conditions: ? output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf ? input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v w: number of wait state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (3 + n) wait insertion TMP1962C10BXBG 2006-02-21 tmp1962-408 (1) read cycle timing, ale width = 0.5 clock cycle, 1 programmed wait state t car t rr t hr t adh t adl t la d0 to d15 t al t cl t ll a le internal clk a d0 to ad15 rd a0 to a15 t acl t ach t lc t rd a 16 to a23 bus cycle = 4 clk cycles s1 s2 s3 s1 w1 t rae 0cs to 3cs w/r TMP1962C10BXBG 2006-02-21 tmp1962-409 (2) read cycle timing, ale width = 1.5 clock cycles, 1 programmed wait state t car t rr t hr t adh t adl t la d0 to d15 t al t cl t ll ale internal clk ad0 to ad15 rd s0 s1 s2 s3 s0 a0 to a15 t acl t ach t lc t rd a16 to a23 w1 t rae 0cs to 3cs w/r bus cycle = 5 clk cycles TMP1962C10BXBG 2006-02-21 tmp1962-410 (3) read cycle timing, ale width = 1.5 clock cycles, 2 externally generated wait states with n = 1 t awl/h a le internal clk a d0 to a d15 rd a d16 to a d23 bus cycle = 6 clk cycles wait d0 to d15 s1 w s2 s3 s0 a0 to a15 w t cw 0cs to 3cs w/r TMP1962C10BXBG 2006-02-21 tmp1962-411 (4) read cycle timing, ale width = 1.5 clock cycles, 4 externally generated wait states with n = 1 t awl/h a le internal clk a d0 to a d15 rd a d16 to a d23 bus cycle = 8 clk cycles wait d0 to d15 s1 s2 s3 s0 a0 to a15 w t cw 0cs to 3cs w/r w w w TMP1962C10BXBG 2006-02-21 tmp1962-412 (5) write cycle timing, ale width = 1.5 clock cycles, zero wait state t ww t car t dw t la d0 to d15 t al t cl t ll a le internal clk a d0 to a d15 wr , hwr 0cs to 3cs w/r a0 to a15 t acl t ach t lc a d16 to a d23 bus cycle = 4 clk cycles t wd TMP1962C10BXBG 2006-02-21 tmp1962-413 22.6.2 separate bus mode (1) dvcc15 = cvcc15 = 1.5 v 0.15 v, dvcc2 = 2.5 v 0.2 v, avcc3m = 3.3 0.2 v, dvcc33 = 3.0 v 0.3 v, ta = ? 20 to 85 c 1. syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-414 2. syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-415 (2) dvcc15 = cvcc15 = 1.5 v 0.15 v, dvcc2 = 2.5 v 0.2 v, avcc3m = 3.3 0.2 v, dvcc33 = 2.5 v 0.2 v, ta = ? 20 to 85 c 1. syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-416 2. syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-417 (3) dvcc15 = cvcc15 = 1.5 v 0.15 v, dvcc2 = 2.5 v 0.2 v, avcc3m = 3.3 0.2 v, dvcc33 = 1.8 v 0.15 v, ta = ? 20 to 85 c 1. syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-418 2. syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-419 (1) read cycle timing (sys cr3 TMP1962C10BXBG 2006-02-21 tmp1962-420 (2) read cycle timing (sys cr3 TMP1962C10BXBG 2006-02-21 tmp1962-421 (3) read cycle timing syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-422 (4) read cycle timing (syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-423 (5) write cycle timing (syscr3 TMP1962C10BXBG 2006-02-21 tmp1962-424 22.7 transfer with dma request the following shows an example of a transfer between the on-chip ram and an external device in multiplex bus mode. ? 16-bit data bus width, non-recovery time ? level data transfer mode ? transfer size of 16 bits, devi ce port size (dps) of 16 bit ? source/destination: on-chip ram/external device the following shows transfer operation timing of the on-chip ram to an external bus during write operation (memory-to-memory transfer). dreqn a le a [23:16] a d [15:0] rd wr hwr csn w/r (n - 2)th transfer (n - 1)th transfer nth transfer (1) (2) (1) indicates the condition under which nth transfer is performed successfully. (2) indicates the condition under which (n + 1)th transfer is not performed. TMP1962C10BXBG 2006-02-21 tmp1962-425 (1) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 2.3 v to 3.3 v, ta = 20 to 85 c (m = 1 to 2) equation 40.5 mhz (fsys) (note) no. parameter symbol (1) min (2) max min max unit 2 rd asserted to dreqn asserted (external device to on-chip ram transfer) tdreq_r wx ? 4.2 (2w + ale + 6) x ? 51 45 195 ns 3 wr / hwr asserted to dreqn asserted (on-chip ram to external device transfer) tdreq_w 0 (2w + ale + 4) x ? 51.8 0 145 ns (2) dvcc2m = fvcc2 = cvcc2 = 2.5 v 0.2 v, fvcc3 = 3.3 v 0.3 v, avcc3m = 3.3 0.2 v, dvcc33 = 1.8 v 0.15 v, ta = 20 to 85 c (m = 1 to 2) equation 40.5 mhz (fsys) (note) no. parameter symbol (1) min (2) max min max unit 2 rd asserted to dreqn asserted (external device to on-chip ram transfer) tdreq_r wx ? 6.2 (2w + ale + 6) x ? 56 43 190 ns 3 wr / hwr asserted to dreqn asserted (on-chip ram to external device transfer) tdreq_w 0 (2w + ale + 4) x ? 56.8 0 140 ns w: number of wait-state cycles inserted. in the case of (1 + n) externally generated wait states with n = 1, w becomes 2. ale: apply ale = 0 for ale 0.5 clock, ale = 1 for ale 1.5 clock. the values in the above table are obtained with w = 2, ale = 0. TMP1962C10BXBG 2006-02-21 tmp1962-426 22.8 serial channel timing (1) i/o interface mode (dvcc3n = 3.0 v 0.3v) in the table below, the letter x represents the fsys cycle period, which varies, depending on the programming of the clock gear function. 1. sclk input mode (sio0 to sio6) equation 40.5 mhz parameter symbol min max min max unit sclk period t scy 12x 296 ns txd data to sclk rise of fall * t oss 2x ? 45 4 ns txd data hold after sclk rise or fall * t ohs 8x ? 15 182 ns rxd data valid to sclk rise or fall * t srd 30 30 ns rxd data hold after sclk rise or fall * t hsr 2x ? 30 19 ns * sclk rise or fall: measured relative to the programmed active edge of sclk. 2. sclk output mode (sio0 to sio6) equation 40.5 mhz parameter symbol min max min max unit sclk period (programmable) t scy 8x 197 ns txd data to sclk rise t oss 4x ? 10 88 ns txd data hold after sclk rise t ohs 4x ? 10 88 ns rxd data valid to sclk rise t srd 45 45 ns rxd data hold after sclk rise t hsr 0 0 ns TMP1962C10BXBG 2006-02-21 tmp1962-427 (2) i/o interface mode (dvcc3n = 2.5 v 0.2 v) in the table below, the letter x represents the fsys cycle period, which varies, depending on the programming of the clock gear function. 1. sclk input mode (sio0 to sio6) equation 40.5 mhz parameter symbol min max min max unit sclk period t scy 16x 395 ns txd data to sclk rise of fall * t oss 4x ? 60 38 ns txd data hold after sclk rise or fall * t ohs 10x ? 15 232 ns rxd data valid to sclk rise or fall * t srd 30 30 ns rxd data hold after sclk rise or fall * t hsr 2x + 10 59 ns * sclk rise or fall: measured relative to the programmed active edge of sclk. 2. sclk output mode (sio0 to sio6) equation 40.5 mhz parameter symbol min max min max unit sclk period (programmable) t scy 8x 197 ns txd data to sclk rise t oss 4x ? 10 88 ns txd data hold after sclk rise t ohs 4x ? 10 88 ns rxd data valid to sclk rise t srd 60 60 ns rxd data hold after sclk rise t hsr 0 0 ns output data txd input data rxd sclk sck output mode/ active-high scl input mode 0 valid t oss t ohs 12 3 t srd t hsr 0 1 23 valid valid valid sclk active-low sck in p ut mode t scy TMP1962C10BXBG 2006-02-21 tmp1962-428 22.9 sbi timing (1) i2c mode in the table below, the letters x and t represent the fsys and t0 cycle periods, respectively. the letter n denotes the value of n programmed into the sck[2:0] (scl output frequency select) field in the sbi0cr1. equation standard mode f sys = 8 mhz n = 4 fast mode f sys = 32 mhz n = 4 parameter symbol min max min max min max unit scl clock frequency t scl 0 0 100 0 400 khz hold time for start condition t hd:sta 4.0 0.6 s scl clock low width (input) (note 1) t low 4.7 1.3 s scl clock high width (output) (note 2) t high 4.0 0.6 s setup time for a repeated start condition t su;sta (note 5) 4.7 0.6 s data hold time (input) (note 3, 4) t hd;dat 0.0 0.0 s data setup time t su;dat 250 100 ns setup time for stop condition t su;sto 4.0 0.6 s bus free time between stop and start conditions t buf (note 5) 4.7 1.3 s note 1: scl clock low width (output) is calculated with (2 (n ? 1) + 4) t. standard mode: 6 sec ? typ (fsys = 8 mhz, n = 4) fast mode: 1.5 sec ? typ (fsys = 32 mhz, n = 4) note 2: scl clock high width (output) is calculated with (2 (n ? 1)) t. standard mode: 4 sec ? typ (fsys = 8mhz, n = 4) fast mode: 1 sec ? typ (fsys = 32 mhz, n = 4) note 3: the output data hold time is equal to 12x. note 4: the philips i 2 c-bus specification states that a device must internally provide a hold time of at least 300 ns for the sda signal to bridge the undefined region of the fall edge of scl. however, TMP1962C10BXBG sbi does not satisfy this requ irement. also, the output buffer for scl does not incorporate slope control of the falling edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the scl and sda lines. note 5: software-dependent sda scl t low t hd;sta t scl t high t r t su;dat t hd;dat t su;sta t su;sto t buf s: start condition sr: repeated start condition p: stop condition t f ss r p note 6: to operate the sbi in i 2 c fast mode, the fysy frequency must be no less than 20 mhz. to operate the sbi in i 2 c standard mode, the fsys frequency must be no less than 4 mhz. TMP1962C10BXBG 2006-02-21 tmp1962-429 (2) clock-synchronous 8-bit sio mode in the table below, the letters x and t represent the fsys and t0 cycle periods, respectively. the letter n denotes the value of n programmed into the sck[2:0] (scl output frequency select) field in the sbi0cr1. the electrical specifications below are for an sck signal with a 50% duty cycle. 1. sck input mode equation 40.5 mhz parameter symbol min max min max unit sck period t scy 16x 395 ns so data to sck rise t oss (t scy /2) ? (6x + 30) 19 ns so data hold after sck rise t ohs (t scy /2) + 4x 296 ns si data valid to sck rise t srd 0 0 ns si data hold after sck rise t hsr 4x + 10 108 ns 2. sck output mode equation 32 mhz parameter symbol min max min max unit sck period (programmable) t scy 2 n ? t 1000 ns so data to sck rise t oss (t scy /2) ? 20 480 ns so data hold after sck rise t ohs (t scy /2) ? 20 480 ns si data valid to sck rise t srd 2x + 30 92 ns si data hold after sck rise t hsr 0 0 ns output data txd input data txd sclk 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid TMP1962C10BXBG 2006-02-21 tmp1962-430 22.10 event counter in the table below, the letter x represents the fsys cycle period. equation 40.5 mhz parameter symbol min max min max unit clock low pulse width t vckl 2x + 100 149 ns clock high pulse width t vckh 2x + 100 149 ns 22.11 timer capture in the table below, the letter x represents the fsys cycle period. equation 40.5 mhz parameter symbol min max min max unit low pulse width t cpl 2x + 100 149 ns high pulse width t cph 2x + 100 149 ns 22.12 general interrupts in the table below, the letter x represents the fsys cycle period. equation 40.5 mhz parameter symbol min max min max unit low pulse width for int0-inta t intal x + 100 125 ns high pulse width for int0-inta t intah x + 100 125 ns 22.13 nmi and stop wake-up interrupts equation 40.5 mhz parameter symbol min max min max unit low pulse width for nmi and int0-int4 t intbl 100 100 ns high pulse width for int0-int4 t intbh 100 100 ns 22.14 scout pin equation 40.5 mhz parameter symbol min max min max unit clock high pulse width t sch 0.5t ? 5 7.4 ns clock low pulse width t scl 0.5t ? 5 7.4 ns note: in the above table, the letter t represents the cycle period of the scout output clock. t sch t scl scout TMP1962C10BXBG 2006-02-21 tmp1962-431 22.15 bus request and bus acknowledge signals t aba (note 1) busrq a le a 0 to a23, rd , wr busak cs0 to cs3 , w/r , hwr a d0 to ad15 t baa (note 2) (note 2) equation 40.5 mhz parameter symbol min max min max unit bus float to busak asserted t aba 0 80 0 80 ns bus float after busak negated t baa 0 80 0 80 ns note 1: if the current bus cycle has not terminated due to wait-state insertion, the TMP1962C10BXBG does not respond to busrq until the wait state ends. note 2: this broken line indicates that output buffers are disabled, not that the signals are at indeterminate states. the pin holds the last logic value present at that pin before the bus is relinquished. this is dy namically accomplished through external load capacitances. the equipment manufacturer may maintain the bus at a predefined state by means of off-ch ip restores, but he or she should designconsidering the time (determined by the cr constant) it takes for a signal to reach a desired state. the on-chip, integrated programmable pull-up/pull-down resistors remain active, depending on internal signal states. TMP1962C10BXBG 2006-02-21 tmp1962-432 22.16 kwup input pull-up register inactive equation 40.5 mhz parameter symbol min max min max unit low pulse width for key0-d tky tbl 100 100 ns high pulse width for key0-d tky tbh 100 100 ns static pull-up equation 40.5 mhz parameter symbol min max min max unit low pulse width for key0-d tky tbl 100 100 ns dynamic pull-up equation 40.5 mhz parameter symbol min max min max unit low pulse width for key0-d tkytbl t2 + 100 t2 + 100 ns t2: dynamic pull-up frequency 22.17 dual pulse input equation 40.5mhz parameter symbol min max min max unit dual input pulse period tdcyc 8y 395 ns dual input pulse setup tabs y + 20 70 ns dual input pulse hold tabh y + 20 70 ns y: sampling clock (fsys/2) 22.18 adtrg input equation 40.5 mhz parameter symbol min max min max unit adrg low level pulse width tad l fsysy/2 + 20 32.4 ns adtrg high level pulse interval tadh fsysy/2 + 20 32.4 ns tabs tabh tdcyc b a TMP1962C10BXBG 2006-02-21 tmp1962-433 23. i/o register summary the internal i/o registers occupy 8-kbyte addresses from ffffe000h through ffffffffh. (registers specified as big-endian) 1. ports 2. watchdog timer (wdt) 3. real-time clock (rtc) 4. 8-bit timer 5. 16-bit timer 6. i 2 cbus/serial i/o (sio) 7. uart/serial i/o (sio) 8. 10-bit a/d converter (adc) 9. key on wake-up (kwup) 10. 32-bit input capture 11. 32-bit output compare 12. interrupt controller (intc) 13. dma controller (dmac) 14. chip select (cs)/wait controller 15. clock generator (cg) 16. flash control 17. rom correction table organization mnemonic register name address 7 6 1 0 bit name read/write reset value function access r/w: read/write. the user can r ead and write the register bit. r: read only. w: write only. w*: the user can read and write the register b it, but a read always returns a value of 1. TMP1962C10BXBG 2006-02-21 tmp1962-434 big-endian [1] port address mnemonic address mnemonic address mnemonic address mnemonic fffff000h fffff010h fffff020h fffff030h 1h p0cr 1h p2 1h 1h 2h p1 2h 2h p4fc 2h 3h p0 3h 3h p4cr 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h p1fc 6h p2fc 6h 6h 7h p1cr 7h p2cr 7h 7h 8h 8h p3fc 8h 8h 9h 9h p3cr 9h 9h ah ah ah p6 ah bh bh p3 bh p5 bh ch ch ch p6fc ch dh dh p4 dh p6cr dh eh eh eh p5fc eh fh fh fh p5cr fh address mnemonic address mnemonic address mnemonic address mnemonic fffff040h pa fffff050h pe fffff060h pi fffff070h 1h p9 1h pd 1h ph 1h 2h p8 2h pc 2h pg 2h 3h p7 3h pb 3h pf 3h 4h pacr 4h pecr 4h picr 4h 5h 5h pdcr 5h phcr 5h 6h 6h pccr 6h pgcr 6h 7h 7h pbcr 7h pfcr 7h 8h pafc 8h pefc 8h pifc 8h 9h 9h pdfc 9h phfc 9h ah ah pcfc ah pgfc ah bh bh pbfc bh pffc bh ch ch peode ch ch dh dh pdode dh dh eh eh pcode eh eh fh fh fh pfode fh address mnemonic address mnemonic address mnemonic address mnemonic fffff0c0h pm fffff0d0h fffff0e0h fffff0f0h 1h pl 1h pp 1h 1h 2h pk 2h po 2h 2h 3h pj 3h pn 3h 3h 4h pmcr 4h 4h 4h 5h plcr 5h ppcr 5h 5h 6h pkcr 6h pocr 6h 6h 7h pjcr 7h pncr 7h 7h 8h 8h 8h 8h 9h plfc 9h 9h 9h ah pkfc ah ah ah bh pjfc bh pnfc bh bh ch ch ch ch (reserved) dh dh dh dh (reserved) eh eh eh eh (reserved) fh fh pnode fh fh (reserved) TMP1962C10BXBG 2006-02-21 tmp1962-435 big-endian [2] wdt [3] rtc address mnemonic address mnemonic address mnemonic address mnemonic fffff080h fffff090h fffff0a0h fffff0b0h 1h 1h 1h 1h 2h 2h wdcr 2h 2h 3h 3h wdmod 3h rtccr 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h rtcreg 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh [4] 8-bit timer address mnemonic address mnemonic address mnemonic address mnemonic fffff100h ta1reg fffff110h ta5reg fffff120h ta9reg fffff130h 1h ta0reg 1h ta4reg 1h ta8reg 1h 2h ta01cr 2h ta45cr 2h ta89cr 2h 3h ta01run 3h ta45run 3h ta89run 3h 4h tag0st 4h tag1st 4h tag2st 4h 5h tag0im 5h tag1im 5h tag2im 5h 6h ta1ffcr 6h ta5ffcr 6h ta9ffcr 6h 7h ta01mod 7h ta45mod 7h ta89mod 7h 8h ta3reg 8h ta7reg 8h tabreg 8h 9h ta2reg 9h ta6reg 9h taareg 9h ah ta23cr ah ta67cr ah taabcr ah bh ta23run bh ta67run bh taabrun bh ch (reserved) ch (reserved) ch (reserved) ch dh (reserved) dh (reserved) dh (reserved) dh eh ta3ffcr eh ta7ffcr eh tabffcr eh fh ta23mod fh ta67mod fh taabmod fh [5] 16-bit timer address mnemonic address mnemonic address mnemonic address mnemonic fffff140h tb0ffcr fffff150h tb1ffcr fffff160h tb2ffcr fffff170h tb3ffcr 1h tb0mod 1h tb1mod 1h tb2mod 1h tb3mod 2h tb0cr 2h tb1cr 2h tb2cr 2h tb3cr 3h tb0run 3h tb1run 3h tb2run 3h tb3run 4h (reserved) 4h (reserved) 4h (reserved) 4h (reserved) 5h (reserved) 5h (reserved) 5h (reserved) 5h (reserved) 6h 6h 6h 6h 7h tb0st 7h tb1st 7h tb2st 7h tb3st 8h tb0rg1h 8h tb1rg1h 8h tb2rg1h 8h tb3rg1h 9h tb0rg1l 9h tb1rg1l 9h tb2rg1l 9h tb3rg1l ah tb0rg0h ah tb1rg0h ah tb2rg0h ah tb3rg0h bh tb0rg0l bh tb1rg0l bh tb2rg0l bh tb3rg0l ch tb0cp1h ch tb1cp1h ch tb2cp1h ch tb3cp1h dh tb0cp1l dh tb1cp1l dh tb2cp1l dh tb3cp1l eh tb0cp0h eh tb1cp0h eh tb2cp0h eh tb3cp0h fh tb0cp0l fh tb1cp0l fh tb2cp0l fh tb3cp0l TMP1962C10BXBG 2006-02-21 tmp1962-436 big-endian address mnemonic address mnemonic address mnemonic address mnemonic fffff180h fffff190h fffff1a0h fffff1b0h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh address mnemonic address mnemonic address mnemonic address mnemonic fffff1c0h fffff1d0h fffff1e0h fffff1f0h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh address mnemonic address mnemonic address mnemonic address mnemonic fffff200h fffff210h fffff220h fffff230h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-437 big-endian address mnemonic fffff240h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh [6] i 2 c/sio [7] uart/sio address mnemonic address mnemonic address mnemonic address mnemonic fffff250h sbicr2/sr fffff260h br0cr fffff270h br2cr fffff280h br4cr 1h i2car 1h sc0mod0 1h sc2mod0 1h sc4mod0 2h sbidbr 2h sc0cr 2h sc2cr 2h sc4cr 3h sbicr1 3h sc0buf 3h sc2buf 3h sc4buf 4h sbicr0 4h 4h 4h 5h 5h sc0mod2 5h sc2mod2 5h sc4mod2 6h sbibr1 6h sc0mod1 6h sc2mod1 6h sc4mod1 7h sbibr0 7h br0add 7h br2add 7h br4add 8h 8h br1cr 8h br3cr 8h br5cr 9h 9h sc1mod0 9h sc3mod0 9h sc5mod0 ah ah sc1cr ah sc3cr ah sc5cr bh bh sc1buf bh sc3buf bh sc5buf ch ch ch ch dh dh sc1mod2 dh sc3mod2 dh sc5mod2 eh eh sc1mod1 eh sc3mod1 eh sc5mod1 fh fh br1add fh br3add fh br5add address mnemonic fffff290h br6cr 1h sc6mod0 2h sc6cr 3h sc6buf 4h 5h sc6mod2 6h sc6mod1 7h br6add 8h 9h ah bh ch dh eh fh TMP1962C10BXBG 2006-02-21 tmp1962-438 big-endian [8] 10-bit adc [9] kwup address mnemonic address mnemonic address mnemonic address mnemonic fffff300h adreg19h fffff310h fffff360h kwupst3 fffff370h 1h adreg19l 1h 1h kwupst2 1h 2h adreg08h 2h 2h kwupst1 2h kwupcnt 3h adreg08l 3h 3h kwupst0 3h kwupclr 4h adreg3bh 4h 4h kwupst7 4h 5h adreg3bl 5h 5h kwupst6 5h 6h adreg2ah 6h adcomregh 6h kwupst5 6h 7h adreg2al 7h adcomregl 7h kwupst4 7h 8h adreg5dh 8h admod3 8h kwupstb 8h 9h adreg5dl 9h (reserved) 9h kwupsta 9h ah adreg4ch ah admod1 ah kwupst9 ah bh adreg4cl bh admod0 bh kwupst8 bh ch adreg7fh ch adclk ch ch dh adreg7fl dh dh dh eh adreg6eh eh eh kwupstd eh fh adreg6el fh admod4 fh kwupstc fh [10] 32-bit input capture address mnemonic address mnemonic address mnemonic address mnemonic fffff400h fffff410h fffff420h fffff430h 1h tbtcr 1h 1h 1h 2h tbtrun 2h 2h 2h 3h tccr 3h cap0cr 3h cap2cr 3h cap4cr 4h tbtcap3 4h tccap0hh 4h tccap2hh 4h tccap4hh 5h tbtcap2 5h tccap0hl 5h tccap2hl 5h tccap4hl 6h tbtcap1 6h tccap0lh 6h tccap2lh 6h tccap4lh 7h tbtcap0 7h tccap0ll 7h tccap2ll 7h tccap4ll 8h tcg1st 8h 8h 8h 9h tcg1im 9h 9h 9h ah tcg0st ah ah ah bh tcg0im bh cap1cr bh cap3cr bh cap5cr ch ch tccap1hh ch tccap3hh ch tccap5hh dh dh tccap1hl dh tccap3hl dh tccap5hl eh eh tccap1lh eh tccap3lh eh tccap5lh fh fh tccap1ll fh tccap3ll fh tccap5ll [11] 32-bit output compare address mnemonic address mnemonic address mnemonic address mnemonic fffff440h fffff450h tccmp0hh fffff460h tccmp4hh fffff470h cmpctl3 1h 1h tccmp0hl 1h tccmp4hl 1h cmpctl2 2h 2h tccmp0lh 2h tccmp4lh 2h cmpctl1 3h cap6cr 3h tccmp0ll 3h tccmp4ll 3h cmpctl0 4h tccap6hh 4h tccmp1hh 4h tccmp5hh 4h cmpctl7 5h tccap6hl 5h tccmp1hl 5h tccmp5hl 5h cmpctl6 6h tccap6lh 6h tccmp1lh 6h tccmp5lh 6h cmpctl5 7h tccap6ll 7h tccmp1ll 7h tccmp5ll 7h cmpctl4 8h 8h tccmp2hh 8h tccmp6hh 8h 9h 9h tccmp2hl 9h tccmp6hl 9h ah ah tccmp2lh ah tccmp6lh ah bh cap7cr bh tccmp2ll bh tccmp6ll bh ch tccap7hh ch tccmp3hh ch tccmp7hh ch dh tccap7hl dh tccmp3hl dh tccmp7hl dh eh tccap7lh eh tccmp3lh eh tccmp7lh eh fh tccap7ll fh tccmp3ll fh tccmp7ll fh TMP1962C10BXBG 2006-02-21 tmp1962-439 big-endian [12] intc address mnemonic address mnemonic address mnemonic address mnemonic ffffe000h imc0h ffffe010h imc4h ffffe020h imc8h ffffe030h imcch 1h 1h 1h 1h 2h imc0l 2h imc4l 2h imc8l 2h imccl 3h 3h 3h 3h 4h imc1h 4h imc5h 4h imc9h 4h imcdh 5h 5h 5h 5h 6h imc1l 6h imc5l 6h imc9l 6h imcdl 7h 7h 7h 7h 8h imc2h 8h imc6h 8h imcah 8h imceh 9h 9h 9h 9h ah imc2l ah imc6l ah imcal ah imcel bh bh bh bh ch imc3h ch imc7h ch imcbh ch imcfh dh dh dh dh eh imc3l eh imc7l eh imcbl eh imcfl fh fh fh fh address mnemonic address mnemonic address mnemonic address mnemonic ffffe040h hivr ffffe050h ffffe060h intclr ffffe070h 1h 1h 1h 1h 2h livr 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-440 big-endian [13] damc address mnemonic address mnemonic address mnemonic address mnemonic ffffe200h ccr0h ffffe210h bcr0h ffffe220h ccr1h ffffe230h bcr1h 1h 1h 1h 1h 2h ccr0l 2h bcr0l 2h ccr1l 2h bcr1l 3h 3h 3h 3h 4h csr0h 4h 4h csr1h 4h 5h 5h 5h 5h 6h csr0l 6h 6h csr1l 6h 7h 7h 7h 7h 8h sar0h 8h dtcr0h 8h sar1h 8h dtcr1h 9h 9h 9h 9h ah sar0l ah dtcr0l ah sar1l ah dtcr1l bh bh bh bh ch dar0h ch ch dar1h ch dh dh dh dh eh dar0l eh eh dar1l eh fh fh fh fh address mnemonic address mnemonic address mnemonic address mnemonic ffffe240h ccr2h ffffe250h bcr2h ffffe260h ccr3h ffffe270h bcr3h 1h 1h 1h 1h 2h ccr2l 2h bcr2l 2h ccr3l 2h bcr3l 3h 3h 3h 3h 4h csr2h 4h 4h csr3h 4h 5h 5h 5h 5h 6h csr2l 6h 6h csr3l 6h 7h 7h 7h 7h 8h sar2h 8h dtcr2h 8h sar3h 8h dtcr3h 9h 9h 9h 9h ah sar2l ah dtcr2l ah sar3l ah dtcr3l bh bh bh bh ch dar2h ch ch dar3h ch dh dh dh dh eh dar2l eh eh dar3l eh fh fh fh fh address mnemonic address mnemonic address mnemonic address mnemonic ffffe280h ccr4h ffffe290h bcr4h ffffe2a0h ccr5h ffffe2b0h bcr5h 1h 1h 1h 1h 2h ccr4l 2h bcr4l 2h ccr5l 2h bcr5l 3h 3h 3h 3h 4h csr4h 4h 4h csr5h 4h 5h 5h 5h 5h 6h csr4l 6h 6h csr5l 6h 7h 7h 7h 7h 8h sar4h 8h dtcr4h 8h sar5h 8h dtcr5h 9h 9h 9h 9h ah sar4l ah dtcr4l ah sar5l ah dtcr5l bh bh bh bh ch dar4h ch ch dar5h ch dh dh dh dh eh dar4l eh eh dar5l eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-441 big-endian address mnemonic address mnemonic address mnemonic address mnemonic ffffe2c0h ccr6h ffffe2d0h bcr6h ffffe2e0h ccr7h ffffe2f0h bcr7h 1h 1h 1h 1h 2h ccr6l 2h bcr6l 2h ccr7l 2h bcr7l 3h 3h 3h 3h 4h csr6h 4h 4h csr7h 4h 5h 5h 5h 5h 6h csr6l 6h 6h csr7l 6h 7h 7h 7h 7h 8h sar6h 8h dtcr6h 8h sar7h 8h dtcr7h 9h 9h 9h 9h ah sar6l ah dtcr6l ah sar7l ah dtcr7l bh bh bh bh ch dar6h ch ch dar7h ch dh dh dh dh eh dar6l eh eh dar7l eh fh fh fh fh address mnemonic address mnemonic address mnemonic address mnemonic ffffe300h dcrh ffffe310h ffffe320h ffffe330h 1h 1h 1h 1h 2h dcrl 2h 2h 2h 3h 3h 3h 3h 4h rsrh 4h 4h 4h 5h 5h 5h 5h 6h rsrl 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch dhrh ch ch ch dh dh dh dh eh dhrl eh eh eh fh fh fh fh address mnemonic address mnemonic address mnemonic address mnemonic ffffe340h ffffe350h ffffe360h ffffe370h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-442 big- endian [14] cs/wait controller address mnemonic address mnemonic address mnemonic address mnemonic ffffe400h bma0 ffffe410h ffffe480h b01cs ffffe490h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h bma1 4h 4h b23cs 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h bma2 8h 8h bexcs 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch bma3 ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh [15] cg address mnemonic address mnemonic address mnemonic address mnemonic ffffee00h syscr3 ffffee10h imcga3 ffffee20h eicrcg ffffee40h 1h syscr2 1h imcga2 1h 1h 2h syscr1 2h imcga1 2h 2h 3h syscr0 3h imcga0 3h 3h 4h 4h imcgb3 4h 4h 5h 5h imcgb2 5h 5h 6h 6h imcgb1 6h 6h 7h 7h imcgb0 7h 7h 8h 8h imcgc3 8h 8h 9h 9h imcgc2 9h 9h ah ah imcgc1 ah ah bh bh imcgc0 bh bh ch ch imcgd3 ch ch dh dh imcgd2 dh dh eh eh imcgd1 eh eh fh fh imcgd0 fh fh [16] flash control [17] rom correction address mnemonic address mnemonic address mnemonic address mnemonic ffffe510h seqmod ffffe520h flcs fff fe540h addreg0 ffffe550h addreg4 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h seqcnt 4h 4h addreg1 4h addreg5 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h addreg2 8h addreg6 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch addreg3 ch addreg7 dh dh dh dh eh eh eh eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-443 little-endian [1] port adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff000h p0 fffff010h fffff020h p4cr fffff030h 1h p1 1h 1h p4fc 1h 2h p0cr 2h p2 2h 2h 3h 3h 3h 3h 4h p1cr 4h p2cr 4h 4h 5h p1fc 5h p2fc 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h p3 8h p5 8h 9h 9h 9h p6 9h ah ah p3cr ah ah bh bh p3fc bh bh ch ch ch p5cr ch dh dh dh p5fc dh eh eh p4 eh p6cr eh fh fh fh p6fc fh adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff040h p7 fffff050h pb fffff060h pf fffff070h 1h p8 1h pc 1h pg 1h 2h p9 2h pd 2h ph 2h 3h pa 3h pe 3h pi 3h 4h 4h pbcr 4h pfcr 4h 5h 5h pccr 5h pgcr 5h 6h 6h pdcr 6h phcr 6h 7h pacr 7h pecr 7h picr 7h 8h 8h pbfc 8h pffc 8h 9h 9h pcfc 9h pgfc 9h ah ah pdfc ah phfc ah bh pafc bh pefc bh pifc bh ch ch ch pfode ch dh dh pcode dh dh eh eh pdode eh eh fh fh peode fh fh adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff0c0h pj fffff0d0h pn fffff0e0h fffff0f0h 1h pk 1h po 1h 1h 2h pl 2h pp 2h 2h 3h pm 3h 3h 3h 4h pjcr 4h pncr 4h 4h 5h pkcr 5h pocr 5h 5h 6h plcr 6h ppcr 6h 6h 7h pmcr 7h 7h 7h 8h pjfc 8h pnfc 8h 8h 9h pkfc 9h pofc 9h 9h ah plfc ah ppfc ah ah bh pmfc bh bh bh ch ch pnode ch ch (reserved) dh dh dh dh (reserved) eh eh eh eh (reserved) fh fh fh fh (reserved) TMP1962C10BXBG 2006-02-21 tmp1962-444 little-endian [2] wdt [3] rtc adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff080h fffff090h wdmod fffff0a0h rtccr fffff0b0h 1h 1h wdcr 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h rtcreg 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh [4] 8-bit timer adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff100h ta01run fffff110h ta45run fffff120h ta89run fffff130h 1h ta01cr 1h ta45cr 1h ta89cr 1h 2h ta0reg 2h ta4reg 2h ta8reg 2h 3h ta1reg 3h ta5reg 3h ta9reg 3h 4h ta01mod 4h ta45mod 4h ta89mod 4h 5h ta1ffcr 5h ta5ffcr 5h ta9ffcr 5h 6h tag0im 6h tag1im 6h tag2im 6h 7h tag0st 7h tag1st 7h tag2st 7h 8h ta23run 8h ta67run 8h taabrun 8h 9h ta23cr 9h ta67cr 9h taabcr 9h ah ta2reg ah ta6reg ah taareg ah bh ta3reg bh ta7reg bh tabreg bh ch ta23mod ch ta67mod ch taabmod ch dh ta3ffcr dh ta7ffcr dh tabffcr dh eh (reserved) eh (reserved) eh (reserved) eh fh (reserved) fh (reserved) fh (reserved) fh [5] 16-bit timer adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff140h tb0run fffff150h tb1run fffff160h tb2run fffff170h tb3run 1h tb0cr 1h tb1cr 1h tb2cr 1h tb3cr 2h tb0mod 2h tb1mod 2h tb2mod 2h tb3mod 3h tb0ffcr 3h tb1ffcr 3h tb2ffcr 3h tb3ffcr 4h tb0st 4h tb1st 4h tb2st 4h tb3st 5h 5h 5h 5h 6h (reserved) 6h (reserved) 6h (reserved) 6h (reserved) 7h (reserved) 7h (reserved) 7h (reserved) 7h (reserved) 8h tb0rg0l 8h tb1rg0l 8h tb2rg0l 8h tb3rg0l 9h tb0rg0h 9h tb1rg0h 9h tb2rg0h 9h tb3rg0h ah tb0rg1l ah tb1rg1l ah tb2rg1l ah tb3rg1l bh tb0rg1h bh tb1rg1h bh tb2rg1h bh tb3rg1h ch tb0cp0l ch tb1cp0l ch tb2cp0l ch tb3cp0l dh tb0cp0h dh tb1cp0h dh tb2cp0h dh tb3cp0h eh tb0cp1l eh tb1cp1l eh tb2cp1l eh tb3cp1l fh tb0cp1h fh tb1cp1h fh tb2cp1h fh tb3cp1h TMP1962C10BXBG 2006-02-21 tmp1962-445 little-endian adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff180h fffff190h fffff1a0h fffff1b0h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff1c0h fffff1d0h fffff1e0h fffff1f0h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff200h fffff210h fffff220h fffff230h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-446 little-endian adr mnemonic fffff240h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh [6] i 2 c/sio [7] uart/sio adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff250h sbicr1 fffff260h sc0buf fffff270h sc2buf fffff280h sc4buf 1h sbidbr 1h sc0cr 1h sc2cr 1h sc4cr 2h i2car 2h sc0mod0 2h sc2mod0 2h sc4mod0 3h sbicr2/sr 3h br0cr 3h br2cr 3h br4cr 4h sbibr0 4h br0add 4h br2add 4h br4add 5h sbibr1 5h sc0mod1 5h sc2mod1 5h sc4mod1 6h 6h sc0mod2 6h sc2mod2 6h sc4mod2 7h 7h 7h 7h 8h 8h sc1buf 8h sc3buf 8h sc5buf 9h 9h sc1cr 9h sc3cr 9h sc5cr ah ah sc1mod0 ah sc3mod0 ah sc5mod0 bh bh br1cr bh br3cr bh br5cr ch ch br1add ch br3add ch br5add dh dh sc1mod1 dh sc3mod1 dh sc5mod1 eh eh sc1mod2 eh sc3mod2 eh sc5mod2 fh fh fh fh adr mnemonic fffff290h sc6buf 1h sc6cr 2h sc6mod0 3h br6cr 4h br6add 5h sc6mod1 6h sc6mod2 7h 8h 9h ah bh ch dh eh fh TMP1962C10BXBG 2006-02-21 tmp1962-447 little-endian [8] 10-bit adc [9] kwup adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff300h adreg08l fffff310h fffff360h kwupst0 fffff370h kwupclr 1h adreg08h 1h 1h kwupst1 1h kwupcnt 2h adreg19l 2h 2h kwupst2 2h 3h adreg19h 3h 3h kwupst3 3h 4h adreg2al 4h adcomregl 4h kwupst4 4h 5h adreg2ah 5h adcomregh 5h kwupst5 5h 6h adreg3bl 6h 6h kwupst6 6h 7h adreg3bh 7h 7h kwupst7 7h 8h adreg4cl 8h admod0 8h kwupst8 8h 9h adreg4ch 9h admod1 9h kwupst9 9h ah adreg5dl ah (reserved) ah kwupsta ah bh adreg5dh bh admod3 bh kwupstb bh ch adreg6el ch admod4 ch kwupstc ch dh adreg6eh dh dh kwupstd dh eh adreg7fl eh eh eh fh adreg7fh fh adclk fh fh [10] 32-bit input capture adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff 400h tccr fffff410h cap0cr fffff420h cap2cr fffff430h cap4cr 1h tbtrun 1h 1h 1h 2h tbtcr 2h 2h 2h 3h 3h 3h 3h 4h tbtcap0 4h tccap0ll 4h tccap2ll 4h tccap4ll 5h tbtcap1 5h tccap0lh 5h tccap2lh 5h tccap4lh 6h tbtcap2 6h tccap0hl 6h tccap2hl 6h tccap4hl 7h tbtcap3 7h tccap0hh 7h tccap2hh 7h tccap4hh 8h tcg0im 8h cap1cr 8h cap3cr 8h cap5cr 9h tcg0st 9h 9h 9h ah tcg1im ah ah ah bh tcg1st bh bh bh ch tcg2im ch tccap1ll ch tccap3ll ch tccap5ll dh tcg2st dh tccap1lh dh tccap3lh dh tccap5lh eh eh tccap1hl eh tccap3hl eh tccap5hl fh fh tccap1hh fh tccap3hh fh tccap5hh [11] 32-bit output compare adr mnemonic adr mnemonic adr mnemonic adr mnemonic fffff 440h cap6cr fffff450h tccmp0ll fffff460h tccmp4ll fffff470h cmpctl0 1h 1h tccmp0lh 1h tccmp4lh 1h cmpctl1 2h 2h tccmp0hl 2h tccmp4hl 2h cmpctl2 3h 3h tccmp0hh 3h tccmp4hh 3h cmpctl3 4h tccap6ll 4h tccmp1ll 4h tccmp5ll 4h 5h tccap6lh 5h tccmp1lh 5h tccmp5lh 5h 6h tccap6hl 6h tccmp1hl 6h tccmp5hl 6h 7h tccap6hh 7h tccmp1hh 7h tccmp5hh 7h 8h cap7cr 8h tccmp2ll 8h tccmp6ll 8h 9h 9h tccmp2lh 9h tccmp6lh 9h ah ah tccmp2hl ah tccmp6hl ah bh bh tccmp2hh bh tccmp6hh bh ch tccap7ll ch tccmp3ll ch tccmp7ll ch dh tccap7lh dh tccmp3lh dh tccmp7lh dh eh tccap7hl eh tccmp3hl eh tccmp7hl eh fh tccap7hh fh tccmp3hh fh tccmp7hh fh little-endian TMP1962C10BXBG 2006-02-21 tmp1962-448 [12] intc adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe000h imc0l ffffe010h imc4l ffffe020h imc8l ffffe030h imccl 1h 1h 1h 1h 2h imc0h 2h imc4h 2h imc8h 2h imcch 3h 3h 3h 3h 4h imc1l 4h imc5l 4h imc9l 4h imcdl 5h 5h 5h 5h 6h imc1h 6h imc5h 6h imc9h 6h imcdh 7h 7h 7h 7h 8h imc2l 8h imc6l 8h imcal 8h imcel 9h 9h 9h 9h ah imc2h ah imc6h ah imcah ah imceh bh bh bh bh ch imc3l ch imc7l ch imcbl ch imcfl dh dh dh dh eh imc3h eh imc7h eh imcbh eh imcfh fh fh fh fh adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe040h hivr ffffe050h ffffe060h intclr ffffe070h 1h 1h 1h 1h 2h livr 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-449 little-endian [13] damc adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe200h ccr0l ffffe210h bcr0l ffffe220h ccr1l ffffe230h bcr1l 1h 1h 1h 1h 2h ccr0h 2h bcr0h 2h ccr1h 2h bcr1h 3h 3h 3h 3h 4h csr0l 4h 4h csr1l 4h 5h 5h 5h 5h 6h csr0h 6h 6h csr1h 6h 7h 7h 7h 7h 8h sar0l 8h dtcr0l 8h sar1l 8h dtcr1l 9h 9h 9h 9h ah sar0h ah dtcr0h ah sar1h ah dtcr1h bh bh bh bh ch dar0l ch ch dar1l ch dh dh dh dh eh dar0h eh eh dar1h eh fh fh fh fh adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe240h ccr2l ffffe250h bcr2l ffffe260h ccr3l ffffe270h bcr3l 1h 1h 1h 1h 2h ccr2h 2h bcr2h 2h ccr3h 2h bcr3h 3h 3h 3h 3h 4h csr2l 4h 4h csr3l 4h 5h 5h 5h 5h 6h csr2h 6h 6h csr3h 6h 7h 7h 7h 7h 8h sar2l 8h dtcr2l 8h sar3l 8h dtcr3l 9h 9h 9h 9h ah sar2h ah dtcr1h ah sar3h ah dtcr3h bh bh bh bh ch dar2l ch ch dar3l ch dh dh dh dh eh dar2h eh eh dar3h eh fh fh fh fh adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe280h ccr4l ffffe290h bcr4l ffffe2a0h ccr5l ffffe2b0h bcr5l 1h 1h 1h 1h 2h ccr4h 2h bcr4h 2h ccr5h 2h bcr5h 3h 3h 3h 3h 4h csr4l 4h 4h csr5l 4h 5h 5h 5h 5h 6h csr4h 6h 6h csr5h 6h 7h 7h 7h 7h 8h sar4l 8h dtcr4l 8h sar5l 8h dtcr5l 9h 9h 9h 9h ah sar4h ah dtcr4h ah sar5h ah dtcr5h bh bh bh bh ch dar4l ch ch dar5l ch dh dh dh dh eh dar4h eh eh dar5h eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-450 little-endian adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe2c0h ccr6l ffffe2d0h bcr6l ffffe2e0h ccr7l ffffe2f0h bcr7l 1h 1h 1h 1h 2h ccr6h 2h bcr6h 2h ccr7h 2h bcr7h 3h 3h 3h 3h 4h csr6l 4h 4h csr7l 4h 5h 5h 5h 5h 6h csr6h 6h 6h csr7h 6h 7h 7h 7h 7h 8h sar6l 8h dtcr6l 8h sar7l 8h dtcr7l 9h 9h 9h 9h ah sar6h ah dtcr6h ah sar7h ah dtcr7h bh bh bh bh ch dar6l ch ch dar7l ch dh dh dh dh eh dar6h eh eh dar7h eh fh fh fh fh adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe300h dcrl ffffe310h ffffe320h ffffe330h 1h 1h 1h 1h 2h dcrh 2h 2h 2h 3h 3h 3h 3h 4h rsrl 4h 4h 4h 5h 5h 5h 5h 6h rsrh 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch dhrl ch ch ch dh dh dh dh eh dhrh eh eh eh fh fh fh fh adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe340h ffffe350h ffffe360h ffffe370h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-451 little-endian [14] cs/wait controller adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe400h bma0 ffffe410h ffffe480h b01cs ffffe490h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h bma1 4h 4h b23cs 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h bma2 8h 8h bexcs 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch bma3 ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh [15] cg adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffee00h syscr0 ffffee10h imcga0 ffffee20h eicrcg ffffee40h 1h syscr1 1h imcga1 1h 1h 2h syscr2 2h imcga2 2h 2h 3h syscr3 3h imcga3 3h 3h 4h 4h imcgb0 4h 4h 5h 5h imcgb1 5h 5h 6h 6h imcgb2 6h 6h 7h 7h imcgb3 7h 7h 8h 8h imcgc0 8h 8h 9h 9h imcgc1 9h 9h ah ah imcgc2 ah ah bh bh imcgc3 bh bh ch ch imcgd0 ch ch dh dh imcgd1 dh dh eh eh imcgd2 eh eh fh fh imcgd3 fh fh [16] flash control [17] rom correction adr mnemonic adr mnemonic adr mnemonic adr mnemonic ffffe510h seqmod ffffe520h flcs fff fe540h addreg0 ffffe550h addreg4 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h seqcnt 4h 4h addreg1 4h addreg5 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h addreg2 8h addreg6 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch addreg3 ch addreg7 dh dh dh dh eh eh eh eh fh fh fh fh TMP1962C10BXBG 2006-02-21 tmp1962-452 24. i/o port equivalent-circuit diagrams ? how to read circuit diagrams the circuit diagrams in this chapter are drawn using the same gate symbols as for the 74hcxx series standard cmos logic ics. the signal named stop has a unique function. this signal goes active-high if the cpu sets the halt bit when the stby[1:0] field in the syscr2 register is programmed to 01 (i.e., stop mode) and the drive enable (drve) bit in the same register is cleared. if the drve bit is set, the stop signal remains inactive (at logic 0). ? the input protection circuit has a resistor in the range of several tens to several hundreds of ohms. ? p0 (d0?d7/ad0?ad7), p1 (d8?d15/ad8?a d15, a8?a15), p2 (a16?23, a0?7), p37,p44, p5 (a0?a7), p6 (a8?a15), pa, pb, pi7, pc1, pc4, pc7, pd2, pd5, pe1, pf2?pf7, pg, ph, pj1?pj4, pl, pm, pn1, pn3?pn7, po, pp ? p30 ( rd ), p31 ( wr ), dclk, pcst3?pcst0, sdao/tpc, tdo ? p32?p36, p40?p43 vcc output data p-ch input/output input data output enable stop input enable n-ch output vcc output data stop n-ch input/output input enable vcc output data output enable stop input data vcc programmable pull-up resistor p-ch TMP1962C10BXBG 2006-02-21 tmp1962-453 ? p7 (an0?an7), p8 (an8?an15), p9 (an16?an23) ? pi0?pi6 ( adtrg , int1?inta), pj0 (int0) ? pc0, pc2, pc3,pc5, pc6, pd0, pd1, pd3, pd4, pd6, pe0, pe2, pn0, pn2 ? pd7, pe3?pe7, pk analog input channel select input input data analog input input enable input/output input enable vcc output data output enable stop input data open-drain output enable p-ch n-ch vcc output data p-ch input/output input data output enable stop input enable n-ch schmitt-trigger n-ch input/output input enable vcc output data output enable stop input data vcc programmable pull-up resistor p-ch schmitt-trigger pull- up resistor control TMP1962C10BXBG 2006-02-21 tmp1962-454 ? pf0, pf1 ? nmi , bw0?bw1, plloff , rstpup ? reset ? dreset , dbge , sdi/ dint , tck, tms, tdi ? trst input schmitt-trigger input wdtout reset reset enable schmitt-trigger vcc input debug reset schmitt-trigger vcc input test reset schmitt-trigger input/output input enable vcc output data output enable s t o p input data open-drain output enable p-ch n-ch schmitt-trigger TMP1962C10BXBG 2006-02-21 tmp1962-455 ? x1, x2 ? vrefh, vrefl x2 high-frequency oscillator enable oscillator circuit clock x1 vrefh vrefon vrefl p-ch ladder resistors TMP1962C10BXBG 2006-02-21 tmp1962-456 25. notations, precautions and restrictions 25.1 notations and terms (1) i/o register fields ar e often referred to as TMP1962C10BXBG 2006-02-21 tmp1962-457 (8) undefined bits in i/o registers undefined i/o register bits are read as undefined states. therefore, software must be coded without relying on the states of any undefined bits. (9) electrostatic discharge (esd) sensitivity the following shows esd sensitivity. protect the device from static damage during device development or production stage. for a detailed description on esd, see general safety precautions and usage considerations. ? TMP1962C10BXBG specification sensitivity machine model: mm 200 v human body model: hbm 1500 v ? tmp1962f10axbg specification sensitivity machine model: mm 200 v human body model: hbm 1200 v (10) notations, precautions and restrictions overflow exception problem: if an overflow exception caused a jump to the exception handler and the first instruction in that exception handler caused another exception, the epc register should point to the address of the first instruction in the exception handler. however, the epc re gister might contain the address th at caused the overflow exception. ? problem-causing situation: when, with the instruction pipeline full, an overflow exception was taken at the following sequence of instructions and then the first instruction in the overflow exception handler causes another exception add, addi or sub <= # instruction that causes an overflow jump or branch instruction <= # instruction with a delay slot delay slot note: toshiba?s compiler uses no instructions that could cause an overflow. therefore, this problem does not occur. workaround: don?t place a jump or branch inst ruction immediately following an instruction that could cause an overflow (add, addi or sub). TMP1962C10BXBG 2006-02-21 tmp1962-458 lwl and lwr instructions problem: the lwl or lwr instruction might provide incorrect results. ? problem-causing situation #1: a. the destination of a load instruction (lb, lbu, lh, lhu, lw, lwl or lwr) is identical to that of the lwl or lwr instruction. b. the instruction pipeline is full. (the load instruction and the lwl or lwr instruction will be executed consecutively.) c. the dmac is programmed for data cache snooping. once the load instruction is executed, the dmac initiates a dma transaction. after it has been serviced, the lwl or lwr instruction is executed. this problem occurs when all of these conditions are true. ? problem-causing situation #2: a. the destination of a load instruction (lb, lbu, lh, lhu, lw, lwl or lwr) is identical to that of the lwl or lwr instruction. b. the doze or halt bit in the config register is set to 1 immediately before the load instruction. c. the instruction pipeline is full. (the load in struction and the lwl or lwr instruction will be executed consecutively.) d. after the load instruction is executed, the processor is put in the stop, sleep or idle mode. e. after an interrupt signaling brings the processor out of the stop, sleep or idle mode, the lwl or lwr instruction is executed. note: this applies to the case in which an interrupt signaling does not generate an interrupt upon exit from stop or idle mode. in other words, either the iec bit in the status register is cleared (interrupts disabled), or if the iec bit is set, the priority level of the incoming interrupt signaling is lower than the mask level pr ogrammed in the cmask field in the status register. (exit from stop, sleep or idle mode can be accomplished even with such settings.) this problem occurs when all of these conditions are true. workarounds: to use the lwl or lwr instruction, 1) place a nop between a load instructio n and the lwl or lwr instruction, or 2) disable the data cache snooping of the dmac be fore the lwl or lwr instruction is executed. also, do not put the processor in stop, s leep or idle mode before the lwl or lwr instruction is executed. TMP1962C10BXBG 2006-02-21 tmp1962-459 overflow exception when a dsu probe is used problem: it looks as if an overflow exception caused a jump to the reset and nonmaskable exception vector address (0xbfc0_0000). ? problem-causing situation: when an overflow exception occurs, with the processor connected to a dsu probe note: toshiba?s compiler uses no instructions that could cause an overflow. therefore, this problem does not occur. workaround: don?t place a jump or branch inst ruction immediately following an instruction that could cause an overflow (add, addi or sub). malfunction of using busreq signl in external bus access mode [condition] } in external bus mode, using auto wait insert function (as same as +n wait) } use external bus request signal function (busreq). } for each target product,bus setting mode (multiplex/ separate) z ale width(short/long) . please refer to following table. internal clock ale output (ale=1.5clk) rd output ( normal ) rd output (abnormal ) 4 4 8 8 8 4 4 trd spec not achieve because of 1 minus wait from original insert external bus request (busreq) when starting bus cycle (s0) 4 4 8 8 4 4 (exp: ale band =1.5clk, auto wait = 3 ) |
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